windows的NVSMI包 1.3MB

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资源文件列表:

NVSMI.zip 大约有5个文件

MCU.exe 838.99KB
nvdebugdump.exe 414.95KB
nvidia-smi.1.pdf 99.63KB
nvidia-smi.exe 505.77KB
nvml.dll 901KB

资源介绍:

windows的NVSMI包

<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws1">idia−smi(1) NVIDIA n<span class="_ _1"></span>vidia−smi(1)</span></div><div class="t m0 x1 h3 y2 ff2 fs1 fc0 sc0 ls2 ws1">NA<span class="ls1">ME</span></div><div class="t m0 x2 h2 y3 ff1 fs0 fc0 sc0 ls0 ws1">nv<span class="_ _0"></span><span class="ls1 ws0">idia−smi − NVIDIA System Management Interface program</span></div><div class="t m0 x1 h3 y4 ff2 fs1 fc0 sc0 ls1 ws0">SYNOPSIS</div><div class="t m0 x2 h2 y5 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1">idia-smi [OPTION1 [ARG1]] [OPTION2 [ARG2]] ...</span></div><div class="t m0 x1 h3 y6 ff2 fs1 fc0 sc0 ls1 ws0">DESCRIPTION</div><div class="t m0 x2 h2 y7 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws2">idia-smi (also NVSMI) pro<span class="ws3">vides monitoring and management capabilities for each of NVIDIA's T<span class="_ _2"></span>esla,</span></span></div><div class="t m0 x2 h2 y8 ff1 fs0 fc0 sc0 ls1 ws4">Quadro, GRID and GeForce de<span class="_ _1"></span><span class="ws5">vices from Fermi and higher architecture families. GeF<span class="_ _1"></span>orce Titan series</span></div><div class="t m0 x2 h2 y9 ff1 fs0 fc0 sc0 ls1 ws5">de<span class="_ _1"></span><span class="ws6">vices are supported for most functions with very limited information pro<span class="ws7">vided for the remainder of the</span></span></div><div class="t m0 x2 h2 ya ff1 fs0 fc0 sc0 ls1 ws8">Geforce brand.<span class="_ _3"> </span>NVSMI is a cross platform tool that supports all standard NVIDIA dri<span class="ls3">ve<span class="ls4">r-</span></span>supported Linux</div><div class="t m0 x2 h2 yb ff1 fs0 fc0 sc0 ls1 ws9">distros, as well as 64bit versions of W<span class="_ _1"></span>indo<span class="_ _1"></span>ws starting with W<span class="_ _1"></span>indo<span class="wsa">ws Serv<span class="_ _1"></span>er 2008 R2.<span class="_ _3"> </span>Metrics can be con-</span></div><div class="t m0 x2 h2 yc ff1 fs0 fc0 sc0 ls1 ws0">sumed directly by users via stdout, or provided by ﬁle via CSV and XML formats for scripting purposes.</div><div class="t m0 x2 h2 yd ff1 fs0 fc0 sc0 ls1 wsb">Note that much of the functionality of NVSMI is pro<span class="wsc">vided by the underlying NVML C-based library<span class="_ _2"></span><span class="ls5">.S<span class="_ _4"></span><span class="ls1">ee</span></span></span></div><div class="t m0 x2 h2 ye ff1 fs0 fc0 sc0 ls1 wsd">the NVIDIA de<span class="_ _1"></span><span class="ls3">ve<span class="_ _0"></span><span class="ls1 wse">loper website link belo<span class="_ _1"></span><span class="ls6">wf<span class="_ _5"></span><span class="ls1">or more information about NVML.<span class="_ _3"> </span>NVML-based p<span class="_ _1"></span>ython bind-</span></span></span></span></div><div class="t m0 x2 h2 yf ff1 fs0 fc0 sc0 ls1 ws0">ings are also a<span class="ls7">va</span>ilable.</div><div class="t m0 x2 h2 y10 ff1 fs0 fc0 sc0 ls1 wsf">The output of NVSMI is not guaranteed to be backwards compatible. Ho<span class="_ _1"></span>we<span class="ls3">ve<span class="ls0 ws10">r, b<span class="_ _0"></span></span></span>oth NVML and the</div><div class="t m0 x2 h2 y11 ff1 fs0 fc0 sc0 ls1 ws11">Python bindings are backw<span class="ws12">ards compatible, and should be the ﬁrst choice when writing an<span class="_ _1"></span><span class="ls8">yt<span class="_ _5"></span><span class="ls1">ools that must</span></span></span></div><div class="t m0 x2 h2 y12 ff1 fs0 fc0 sc0 ls1 ws0">be maintained across NVIDIA dri<span class="_ _1"></span><span class="ls3">ve<span class="_ _0"></span><span class="ls9">rr<span class="_ _5"></span><span class="ls1">eleases.</span></span></span></div><div class="t m0 x2 h4 y13 ff2 fs0 fc0 sc0 ls1 ws0">NVML SDK:<span class="_"> </span><span class="ff3">http://developer<span class="_ _6"></span>.n<span class="_ _1"></span>vidia.com/n<span class="_ _1"></span>vidia-mana<span class="lsa">ge</span>ment-library-n<span class="_ _1"></span>vml/</span></div><div class="t m0 x2 h4 y14 ff2 fs0 fc0 sc0 ls1 ws0">Python bindings:<span class="_"> </span><span class="ff3">http://pypi.python.or<span class="_ _1"></span>g/pypi/n<span class="_ _1"></span>vidia-ml-py/</span></div><div class="t m0 x1 h3 y15 ff2 fs1 fc0 sc0 ls1 ws0">OPTIONS</div><div class="t m0 x3 h5 y16 ff2 fs0 fc0 sc0 ls1 ws0">GENERAL OPTIONS</div><div class="t m0 x3 h5 y17 ff2 fs0 fc0 sc0 ls1 ws0">−h, −−help</div><div class="t m0 x2 h2 y18 ff1 fs0 fc0 sc0 ls1 ws0">Print usage information and exit.</div><div class="t m0 x3 h5 y19 ff2 fs0 fc0 sc0 ls1 ws0">SUMMAR<span class="_ _1"></span><span class="ls9">YO<span class="_ _5"></span><span class="ls1">PTIONS</span></span></div><div class="t m0 x3 h5 y1a ff2 fs0 fc0 sc0 ls1 ws0">−L, −−list−gpus</div><div class="t m0 x2 h2 y1b ff1 fs0 fc0 sc0 ls1 ws0">List each of the NVIDIA GPUs in the system, along with their UUIDs.</div><div class="t m0 x3 h5 y1c ff2 fs0 fc0 sc0 lsa ws0">QU<span class="ls1">ER<span class="_ _1"></span><span class="ls9">YO<span class="_ _7"></span><span class="ls1">PTIONS</span></span></span></div><div class="t m0 x3 h5 y1d ff2 fs0 fc0 sc0 ls1 ws0">−q, −−query</div><div class="t m0 x2 h4 y1e ff1 fs0 fc0 sc0 ls1 ws13">Display GPU or Unit info.<span class="_ _8"> </span><span class="ws14">Displayed info includes all data listed in the (<span class="ff3">GPU A<span class="_ _1"></span>TTRIBUTES<span class="ff1 lsb">)o<span class="_ _9"></span>r(<span class="_ _9"></span><span class="ff3 ls1">UNIT</span></span></span></span></div><div class="t m0 x2 h4 y1f ff3 fs0 fc0 sc0 lsc ws14">AT<span class="_ _0"></span><span class="ls1">TRIBUTES<span class="ff1 lsd">)s<span class="_ _a"></span><span class="ls1 ws15">ections of this document.<span class="_ _b"> </span>Some devices and/or en<span class="_ _2"></span><span class="ws16">vironments don't support all possible</span></span></span></span></div><div class="t m0 x2 h2 y20 ff1 fs0 fc0 sc0 ls1 ws17">information. An<span class="lse">yu<span class="_ _9"></span><span class="ls1 ws18">nsupported data is indicated by a "N/A" in the output.<span class="_ _8"> </span><span class="ws19">By default information for all</span></span></span></div><div class="t m0 x2 h2 y21 ff1 fs0 fc0 sc0 ls4 ws19">av<span class="ls1 ws0">ailable GPUs or Units is displayed.<span class="_ _c"> </span>Use the<span class="_"> </span><span class="ff2">−i<span class="_"> </span></span>option to restrict the output to a single GPU or Unit.</span></div><div class="t m0 x3 h5 y22 ff2 fs0 fc0 sc0 ls1 ws0">[plus optional]</div><div class="t m0 x3 h5 y23 ff2 fs0 fc0 sc0 ls1 ws0">−u, −−unit</div><div class="t m0 x2 h2 y24 ff1 fs0 fc0 sc0 ls1 ws0">Display Unit data instead of GPU data.<span class="_ _c"> </span>Unit data is only a<span class="ls7">va</span>ilable for NVIDIA S−class T<span class="_ _2"></span>esla enclosures.</div><div class="t m0 x3 h5 y25 ff2 fs0 fc0 sc0 ls1 ws0">−i, −−id=ID</div><div class="t m0 x2 h2 y26 ff1 fs0 fc0 sc0 ls1 ws1a">Display data for a single speciﬁed GPU or Unit.<span class="_ _3"> </span>The speciﬁed id may be the GPU/Unit's 0−based inde<span class="lsf">xi<span class="_ _d"></span><span class="ls1">n</span></span></div><div class="t m0 x2 h2 y27 ff1 fs0 fc0 sc0 ls1 ws1b">the natural enumeration returned by the dri<span class="_ _1"></span><span class="ls3">ve<span class="_ _0"></span><span class="ls0 ws1c">r, t<span class="_ _0"></span><span class="ls1 ws1d">he GPU's board serial number<span class="_ _1"></span><span class="ls10">,t<span class="_ _9"></span><span class="ls1">he GPU's UUID, or the</span></span></span></span></span></div><div class="t m0 x2 h2 y28 ff1 fs0 fc0 sc0 ls1 ws1e">GPU's PCI bus ID (as domain:b<span class="_ _1"></span>us:device.function in he<span class="_ _1"></span><span class="ws1f">x). It<span class="_ _e"> </span><span class="ws1e">is recommended that users desiring consis-</span></span></div><div class="t m0 x2 h2 y29 ff1 fs0 fc0 sc0 ls1 ws1e">tenc<span class="ls11">yu<span class="_ _d"></span><span class="ls1 ws20">se either UUID or PCI bus ID, since de<span class="_ _1"></span>vice enumeration ordering is not guaranteed to be consistent</span></span></div><div class="t m0 x2 h2 y2a ff1 fs0 fc0 sc0 ls1 ws0">between reboots and board serial number might be shared between multiple GPUs on the same board.</div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1">idia−smi 387.12<span class="_ _f"> </span><span class="ws21">2017/10/3 1</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/bg2.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws1">idia−smi(1) NVIDIA n<span class="_ _1"></span>vidia−smi(1)</span></div><div class="t m0 x3 h5 y2 ff2 fs0 fc0 sc0 ls1 ws0">−f FILE, −−ﬁlename=FILE</div><div class="t m0 x2 h2 y3 ff1 fs0 fc0 sc0 ls1 ws22">Redirect query output to the speciﬁed ﬁle in place of the default stdout.<span class="_ _c"> </span>The speciﬁed ﬁle will be o<span class="ls3">ve</span>rwrit-</div><div class="t m0 x2 h2 y2c ff1 fs0 fc0 sc0 ls1 ws22">ten.</div><div class="t m0 x3 h5 y4 ff2 fs0 fc0 sc0 ls1 ws0">−x, −−xml−f<span class="_ _1"></span>ormat</div><div class="t m0 x2 h2 y5 ff1 fs0 fc0 sc0 ls1 ws23">Produce XML output in place of the default human−readable format.<span class="_ _8"> </span><span class="ws24">Both GPU and Unit query outputs</span></div><div class="t m0 x2 h2 y2d ff1 fs0 fc0 sc0 ls1 ws0">conform to corresponding DTDs.<span class="_ _c"> </span>These are a<span class="ls7">va</span>ilable via the<span class="_"> </span><span class="ff2">−−dtd<span class="_"> </span></span>ﬂag.</div><div class="t m0 x3 h5 y6 ff2 fs0 fc0 sc0 ls1 ws0">−−dtd</div><div class="t m0 x2 h2 y7 ff1 fs0 fc0 sc0 ls1 ws0">Use with<span class="_"> </span><span class="ff2">−x</span><span class="ls12">.E<span class="_ _10"></span><span class="ls1">mbed the DTD in the XML output.</span></span></div><div class="t m0 x3 h5 y2e ff2 fs0 fc0 sc0 ls1 ws0">−−debug=FILE</div><div class="t m0 x2 h2 y2f ff1 fs0 fc0 sc0 ls1 ws0">Produces an encrypted debug log for use in submission of b<span class="_ _1"></span>ugs back to NVIDIA.</div><div class="t m0 x3 h5 y30 ff2 fs0 fc0 sc0 ls1 ws0">−d TYPE, −−display=TYPE</div><div class="t m0 x2 h2 y31 ff1 fs0 fc0 sc0 ls1 ws25">Display only selected information: MEMOR<span class="_ _2"></span><span class="ls13 ws26">Y, U<span class="_ _11"> </span><span class="ls1">TILIZA<span class="_ _6"></span><span class="ws27">TION, ECC, TEMPERA<span class="_ _2"></span>TURE, PO<span class="_ _1"></span>WER,</span></span></span></div><div class="t m0 x2 h2 y32 ff1 fs0 fc0 sc0 ls1 ws28">CLOCK, COMPUTE, PIDS, PERFORMANCE, SUPPOR<span class="_ _2"></span>TED_CLOCKS, P<span class="_ _2"></span><span class="ls0">AG<span class="_ _0"></span><span class="ls1">E_RETIREMENT<span class="_ _1"></span>,</span></span></div><div class="t m0 x2 h2 y33 ff1 fs0 fc0 sc0 ls0 ws28">AC<span class="_ _0"></span><span class="ls1 ws29">COUNTING Flags can be combined with comma e.g.<span class="_ _b"> </span>"MEMOR<span class="_ _2"></span><span class="ls13">Y,<span class="_ _11"> </span><span class="ls1 ws2a">ECC". Sampling<span class="_ _12"> </span><span class="ws29">data with max,</span></span></span></span></div><div class="t m0 x2 h2 y10 ff1 fs0 fc0 sc0 ls1 ws2b">min and avg is also returned for PO<span class="_ _1"></span>WER, UTILIZA<span class="_ _6"></span>TION and CLOCK display types.<span class="_ _13"> </span>Doesn't work with</div><div class="t m0 x2 h2 y11 ff1 fs0 fc0 sc0 ls1 ws0">-u/--unit or -x/--xml-format ﬂags.</div><div class="t m0 x3 h5 y34 ff2 fs0 fc0 sc0 ls1 ws0">−l SEC, −−loop=SEC</div><div class="t m0 x2 h2 y35 ff1 fs0 fc0 sc0 ls1 ws2c">Continuously report query data at the speciﬁed interv<span class="ws2d">al, rather than the def<span class="_ _1"></span>ault of just once.<span class="_ _13"> </span>The applica-</span></div><div class="t m0 x2 h2 y36 ff1 fs0 fc0 sc0 ls1 ws2e">tion will sleep in−between queries.<span class="_ _c"> </span>Note that on Linux ECC error or XID error e<span class="ls3">ve</span><span class="ws2f">nts will print out during</span></div><div class="t m0 x2 h4 y37 ff1 fs0 fc0 sc0 ls1 ws30">the sleep period if the<span class="_"> </span><span class="ff3">-x<span class="_"> </span></span>ﬂag was not speciﬁed.<span class="_ _c"> </span>Pressing Ctrl+C at an<span class="ls14">yt<span class="_ _5"></span><span class="ls1">ime will abort the loop, which will</span></span></div><div class="t m0 x2 h2 y38 ff1 fs0 fc0 sc0 ls1 ws31">otherwise run indeﬁnitely<span class="_ _2"></span><span class="ls15">.I<span class="_ _14"></span><span class="ls16">fn<span class="_ _9"></span>oa<span class="_ _9"></span><span class="ls17">rg<span class="ls1">ument is speciﬁed for the<span class="_"> </span><span class="ff2">−l<span class="_"> </span></span>form a default interv<span class="_ _1"></span><span class="ws32">al of 5 seconds is</span></span></span></span></span></div><div class="t m0 x2 h2 y39 ff1 fs0 fc0 sc0 ls1 ws32">used.</div><div class="t m0 x3 h5 y3a ff2 fs0 fc0 sc0 ls1 ws0">SELECTIVE QUER<span class="_ _1"></span><span class="ls9">YO<span class="_ _5"></span><span class="ls1">PTIONS</span></span></div><div class="t m0 x2 h2 y3b ff1 fs0 fc0 sc0 ls1 ws0">Allows the caller to pass an e<span class="_ _1"></span>xplicit list of properties to query<span class="_ _2"></span>.</div><div class="t m0 x3 h5 y3c ff2 fs0 fc0 sc0 ls1 ws0">[one of]</div><div class="t m0 x3 h5 y3d ff2 fs0 fc0 sc0 ls1 ws0">−−query−gpu=</div><div class="t m0 x2 h2 y3e ff1 fs0 fc0 sc0 ls1 ws33">Information about GPU.<span class="_ _15"> </span><span class="ls3">Pa</span>ss comma separated list of properties you want to query<span class="_ _1"></span><span class="ls18">.e<span class="_ _16"></span><span class="ls1">.g.</span></span></div><div class="t m0 x2 h2 y3f ff1 fs0 fc0 sc0 ls1 ws33">−−query−gpu=pci.b<span class="ws34">us_id,persistence_mode. Call<span class="_ _17"> </span><span class="ws0">−−help−query−gpu for more info.</span></span></div><div class="t m0 x3 h5 y40 ff2 fs0 fc0 sc0 ls1 ws0">−−query−supported−clocks=</div><div class="t m0 x2 h2 y41 ff1 fs0 fc0 sc0 ls1 ws0">List of supported clocks.<span class="_ _c"> </span>Call −−help−query−supported−clocks for more info.</div><div class="t m0 x3 h5 y42 ff2 fs0 fc0 sc0 ls1 ws0">−−query−compute−apps=</div><div class="t m0 x2 h2 y43 ff1 fs0 fc0 sc0 ls1 ws0">List of currently acti<span class="ls3 ws35">ve c</span>ompute processes.<span class="_ _c"> </span>Call −−help−query−compute−apps for more info.</div><div class="t m0 x3 h5 y24 ff2 fs0 fc0 sc0 ls1 ws0">−−query−accounted−apps=</div><div class="t m0 x2 h2 y44 ff1 fs0 fc0 sc0 ls1 ws0">List of accounted compute processes.<span class="_ _c"> </span>Call −−help−query−accounted−apps for more info.</div><div class="t m0 x3 h5 y26 ff2 fs0 fc0 sc0 ls1 ws0">−−query−retir<span class="_ _1"></span>ed−pages=</div><div class="t m0 x2 h2 y27 ff1 fs0 fc0 sc0 ls1 ws0">List of GPU device memory pages that ha<span class="_ _1"></span><span class="ls3 ws35">ve b<span class="ls1 ws0">een retired.<span class="_ _c"> </span>Call −−help−query−retired−pages for more info.</span></span></div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1">idia−smi 387.12<span class="_ _f"> </span><span class="ws21">2017/10/3 2</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws1">idia−smi(1) NVIDIA n<span class="_ _1"></span>vidia−smi(1)</span></div><div class="t m0 x3 h5 y2 ff2 fs0 fc0 sc0 ls1 ws1">[mandatory]</div><div class="t m0 x3 h5 y3 ff2 fs0 fc0 sc0 ls1 ws1">−−format=</div><div class="t m0 x2 h2 y2c ff1 fs0 fc0 sc0 ls1 ws0">Comma separated list of format options:</div><div class="t m0 x2 h2 y45 ff1 fs0 fc0 sc0 ls1 ws0">•<span class="_ _18"> </span>csv - comma separated values (MAND<span class="_ _2"></span><span class="ls19 ws36">AT O<span class="_ _11"> </span><span class="ls1a">RY<span class="_ _0"></span><span class="ls1">)</span></span></span></div><div class="t m0 x2 h2 y46 ff1 fs0 fc0 sc0 ls1 ws0">•<span class="_ _18"> </span>noheader - skip ﬁrst line with column headers</div><div class="t m0 x2 h2 y47 ff1 fs0 fc0 sc0 ls1 ws0">•<span class="_ _18"> </span>nounits - don’<span class="ls9">tp<span class="_ _5"></span><span class="ls1">rint units for numerical v<span class="_ _1"></span>alues</span></span></div><div class="t m0 x3 h5 y48 ff2 fs0 fc0 sc0 ls1 ws0">[plus any of]</div><div class="t m0 x3 h5 y49 ff2 fs0 fc0 sc0 ls1 ws0">−i, −−id=ID</div><div class="t m0 x2 h2 y4a ff1 fs0 fc0 sc0 ls1 ws37">Display data for a single speciﬁed GPU.<span class="_ _13"> </span>The speciﬁed id may be the GPU's 0−based inde<span class="ls1b">xi<span class="_ _19"></span><span class="ls1c">nt<span class="_ _19"></span><span class="ls1 ws38">he natural</span></span></span></div><div class="t m0 x2 h2 y4b ff1 fs0 fc0 sc0 ls1 ws39">enumeration returned by the dri<span class="ls3">ve<span class="ls0 ws3a">r, t<span class="_ _0"></span></span></span>he GPU's board serial number<span class="_ _1"></span><span class="ls1d">,t<span class="_ _5"></span><span class="ls1 ws3b">he GPU's UUID, or the GPU's PCI b<span class="_ _1"></span>us</span></span></div><div class="t m0 x2 h2 y4c ff1 fs0 fc0 sc0 ls1 ws3c">ID (as domain:bus:de<span class="_ _1"></span>vice.function in he<span class="ws3d">x). It<span class="_ _e"> </span></span>is recommended that users desiring consistenc<span class="ls1e">yu<span class="_ _9"></span><span class="ls1 ws3e">se either</span></span></div><div class="t m0 x2 h2 y4d ff1 fs0 fc0 sc0 ls1 ws3f">UUID or PCI bus ID, since de<span class="_ _1"></span><span class="ws40">vice enumeration ordering is not guaranteed to be consistent between reboots</span></div><div class="t m0 x2 h2 y4e ff1 fs0 fc0 sc0 ls1 ws0">and board serial number might be shared between multiple GPUs on the same board.</div><div class="t m0 x3 h5 y4f ff2 fs0 fc0 sc0 ls1 ws0">−f FILE, −−ﬁlename=FILE</div><div class="t m0 x2 h2 y50 ff1 fs0 fc0 sc0 ls1 ws22">Redirect query output to the speciﬁed ﬁle in place of the default stdout.<span class="_ _c"> </span>The speciﬁed ﬁle will be o<span class="ls3">ve</span>rwrit-</div><div class="t m0 x2 h2 y51 ff1 fs0 fc0 sc0 ls1 ws22">ten.</div><div class="t m0 x3 h5 y52 ff2 fs0 fc0 sc0 ls1 ws0">−l SEC, −−loop=SEC</div><div class="t m0 x2 h2 y53 ff1 fs0 fc0 sc0 ls1 ws2c">Continuously report query data at the speciﬁed interv<span class="ws2d">al, rather than the def<span class="_ _1"></span>ault of just once.<span class="_ _13"> </span>The applica-</span></div><div class="t m0 x2 h2 y54 ff1 fs0 fc0 sc0 ls1 ws2e">tion will sleep in−between queries.<span class="_ _c"> </span>Note that on Linux ECC error or XID error e<span class="ls3">ve</span><span class="ws2f">nts will print out during</span></div><div class="t m0 x2 h4 y14 ff1 fs0 fc0 sc0 ls1 ws30">the sleep period if the<span class="_"> </span><span class="ff3">-x<span class="_"> </span></span>ﬂag was not speciﬁed.<span class="_ _c"> </span>Pressing Ctrl+C at an<span class="ls14">yt<span class="_ _5"></span><span class="ls1">ime will abort the loop, which will</span></span></div><div class="t m0 x2 h2 y55 ff1 fs0 fc0 sc0 ls1 ws31">otherwise run indeﬁnitely<span class="_ _2"></span><span class="ls15">.I<span class="_ _14"></span><span class="ls16">fn<span class="_ _9"></span>oa<span class="_ _9"></span><span class="ls17">rg<span class="ls1">ument is speciﬁed for the<span class="_"> </span><span class="ff2">−l<span class="_"> </span></span>form a default interv<span class="_ _1"></span><span class="ws32">al of 5 seconds is</span></span></span></span></span></div><div class="t m0 x2 h2 y56 ff1 fs0 fc0 sc0 ls1 ws32">used.</div><div class="t m0 x3 h5 y17 ff2 fs0 fc0 sc0 ls1 ws0">−lms ms, −−loop−ms=ms</div><div class="t m0 x2 h2 y18 ff1 fs0 fc0 sc0 ls1 ws0">Same as −l,−−loop but in milliseconds.</div><div class="t m0 x3 h5 y19 ff2 fs0 fc0 sc0 ls1 ws0">DEVICE MODIFICA<span class="_ _2"></span>TION OPTIONS</div><div class="t m0 x3 h5 y1a ff2 fs0 fc0 sc0 ls1 ws0">[any one of]</div><div class="t m0 x3 h5 y1b ff2 fs0 fc0 sc0 ls1 ws0">−pm, −−persistence−mode=MODE</div><div class="t m0 x2 h4 y57 ff1 fs0 fc0 sc0 ls1 ws41">Set the persistence mode for the target GPUs.<span class="_ _13"> </span><span class="ws42">See the (<span class="ff3">GPU ATTRIB<span class="_ _1"></span>UTES<span class="ff1 ls1f">)s<span class="_ _9"></span><span class="ls1">ection for a description of</span></span></span></span></div><div class="t m0 x2 h4 y58 ff1 fs0 fc0 sc0 ls1 ws43">persistence mode.<span class="_ _c"> </span>Requires root.<span class="_ _3"> </span><span class="ls0">Wi<span class="_ _0"></span></span>ll impact all GPUs unless a single GPU is speciﬁed using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>argu-</div><div class="t m0 x2 h2 y59 ff1 fs0 fc0 sc0 ls1 ws44">ment. The<span class="_ _e"> </span>ef<span class="_ _1"></span><span class="ws45">fect of this operation is immediate.<span class="_ _8"> </span>Ho<span class="_ _1"></span>we<span class="ls3">ve<span class="ls0 ws46">r, i<span class="_ _0"></span><span class="ls20">td<span class="_ _19"></span><span class="ls1 ws45">oes not persist across reboots.<span class="_ _13"> </span>After each</span></span></span></span></span></div><div class="t m0 x2 h2 y5a ff1 fs0 fc0 sc0 ls1 ws0">reboot persistence mode will default to "Disabled".<span class="_ _c"> </span><span class="ls21 ws47">Av a<span class="_"> </span></span>ilable on Linux only<span class="_ _1"></span>.</div><div class="t m0 x3 h5 y20 ff2 fs0 fc0 sc0 ls1 ws0">−e, −−ecc−conﬁg=CONFIG</div><div class="t m0 x2 h4 y21 ff1 fs0 fc0 sc0 ls1 ws48">Set the ECC mode for the target GPUs.<span class="_ _8"> </span><span class="ws49">See the (<span class="ff3">GPU A<span class="_ _1"></span>TTRIBUTES<span class="ff1 ls22">)s<span class="_ _9"></span><span class="ls1">ection for a description of ECC</span></span></span></span></div><div class="t m0 x2 h4 y5b ff1 fs0 fc0 sc0 ls1 ws4a">mode. Requires<span class="_ _1a"> </span>root. W<span class="_ _1"></span><span class="ws4b">ill impact all GPUs unless a single GPU is speciﬁed using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>ar<span class="ws4c">gument. This</span></span></div><div class="t m0 x2 h2 y42 ff1 fs0 fc0 sc0 ls1 ws0">setting takes ef<span class="_ _1"></span>fect after the next reboot and is persistent.</div><div class="t m0 x3 h5 y24 ff2 fs0 fc0 sc0 ls1 ws0">−p, −−reset−ecc−err<span class="_ _1"></span>ors=TYPE</div><div class="t m0 x2 h4 y44 ff1 fs0 fc0 sc0 ls1 ws4d">Reset the ECC error counters for the target GPUs.<span class="_ _3"> </span>See the (<span class="ff3">GPU ATTRIB<span class="_ _1"></span>UTES<span class="ff1 ls23">)s<span class="_ _d"></span><span class="ls1 ws4e">ection for a description</span></span></span></div><div class="t m0 x2 h2 y5c ff1 fs0 fc0 sc0 ls1 ws4f">of ECC error counter types.<span class="_ _b"> </span><span class="ls21 ws47">Av a<span class="_"> </span></span><span class="ws50">ilable arguments are 0|V<span class="_ _1"></span>OLA<span class="_ _6"></span>TILE or 1|AGGREGA<span class="_ _6"></span><span class="ws51">TE. Requires<span class="_ _12"> </span>root.</span></span></div><div class="t m0 x2 h4 y5d ff1 fs0 fc0 sc0 ls0 ws51">Wi<span class="_ _0"></span><span class="ls1 ws52">ll impact all GPUs unless a single GPU is speciﬁed using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>ar<span class="ws53">gument. The<span class="_ _1a"> </span>ef<span class="_ _1"></span><span class="ws54">fect of this operation</span></span></span></div><div class="t m0 x2 h2 y5e ff1 fs0 fc0 sc0 ls1 ws0">is immediate.</div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1">idia−smi 387.12<span class="_ _f"> </span><span class="ws21">2017/10/3 3</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/bg4.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws1">idia−smi(1) NVIDIA n<span class="_ _1"></span>vidia−smi(1)</span></div><div class="t m0 x3 h5 y2 ff2 fs0 fc0 sc0 ls1 ws0">−c, −−compute−mode=MODE</div><div class="t m0 x2 h4 y3 ff1 fs0 fc0 sc0 ls1 ws55">Set the compute mode for the target GPUs.<span class="_ _c"> </span>See the (<span class="ff3">GPU ATTRIB<span class="_ _1"></span>UTES<span class="ff1 ls24">)s<span class="_ _5"></span><span class="ls1">ection for a description of com-</span></span></span></div><div class="t m0 x2 h4 y2c ff1 fs0 fc0 sc0 ls1 ws56">pute mode.<span class="_ _13"> </span>Requires root.<span class="_ _3"> </span><span class="ls0">Wi<span class="_ _0"></span></span>ll impact all GPUs unless a single GPU is speciﬁed using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>argument.</div><div class="t m0 x2 h2 y5f ff1 fs0 fc0 sc0 ls1 ws57">The ef<span class="_ _1"></span>fect of this operation is immediate.<span class="_ _8"> </span>Ho<span class="_ _1"></span>we<span class="ls3">ve<span class="ls0 ws58">r, i<span class="_ _0"></span><span class="ls25">td<span class="_ _19"></span><span class="ls1 ws57">oes not persist across reboots.<span class="_ _13"> </span><span class="ws59">After each reboot</span></span></span></span></span></div><div class="t m0 x2 h2 y60 ff1 fs0 fc0 sc0 ls1 ws0">compute mode will reset to "DEF<span class="_ _2"></span><span class="ls26">AU<span class="_ _1b"></span><span class="ls27">LT<span class="_ _1c"></span><span class="ls1">".</span></span></span></div><div class="t m0 x3 h5 y2d ff2 fs0 fc0 sc0 ls1 ws0">−dm TYPE, −−dri<span class="lsa">ve</span>r−model=TYPE</div><div class="t m0 x3 h5 y61 ff2 fs0 fc0 sc0 ls1 ws0">−fdm TYPE, −−f<span class="_ _1"></span>orce−dri<span class="lsa">ve</span>r−model=TYPE</div><div class="t m0 x2 h4 y62 ff1 fs0 fc0 sc0 ls1 ws5a">Enable or disable TCC dri<span class="_ _1"></span><span class="ls3">ve<span class="_ _0"></span><span class="ls28">rm<span class="_ _d"></span><span class="ls1 ws5b">odel. F<span class="ws5a">or W<span class="_ _1"></span>indo<span class="_ _1"></span>ws only<span class="_ _2"></span><span class="ls29">.R<span class="_ _10"></span><span class="ls1 ws5c">equires administrator pri<span class="_ _1"></span>vileges.<span class="_ _3"> </span><span class="ff3">−dm<span class="_"> </span></span>will fail</span></span></span></span></span></span></div><div class="t m0 x2 h4 y63 ff1 fs0 fc0 sc0 ls1 ws5d">if a display is attached, but<span class="_"> </span><span class="ff3">−fdm<span class="_"> </span></span>will force the dri<span class="_ _1"></span><span class="ls3">ve<span class="ls2a">rm<span class="_ _5"></span><span class="ls1 ws5e">odel to change.<span class="_ _3"> </span><span class="ls0">Wi<span class="_ _0"></span></span>ll impact all GPUs unless a sin-</span></span></span></div><div class="t m0 x2 h4 y64 ff1 fs0 fc0 sc0 ls1 ws5f">gle GPU is speciﬁed using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>ar<span class="ws60">gument. A<span class="_ _1d"> </span><span class="ws20">reboot is required for the change to tak<span class="ls11">ep<span class="_ _d"></span><span class="ls1 ws61">lace. See<span class="_ _1a"> </span><span class="ff2">Dri<span class="lsa">ve</span>r</span></span></span></span></span></div><div class="t m0 x2 h2 y65 ff2 fs0 fc0 sc0 ls1 ws61">Model<span class="_ _17"> </span><span class="ff1 ws0">for more information on Windo<span class="_ _1"></span>ws dri<span class="_ _1"></span><span class="ls3">ve<span class="ls9">rm<span class="_ _7"></span><span class="ls1">odels.</span></span></span></span></div><div class="t m0 x4 h5 yb ff2 fs0 fc0 sc0 ls1 ws0">−−gom=MODE</div><div class="t m0 x2 h2 yc ff1 fs0 fc0 sc0 ls1 ws62">Set GPU Operation Mode: 0/ALL_ON, 1/COMPUTE, 2/LO<span class="_ _1"></span><span class="ws63">W_DP Supported on GK110 M-class and X-</span></div><div class="t m0 x2 h2 y66 ff1 fs0 fc0 sc0 ls1 ws64">class T<span class="_ _2"></span>esla products from the K<span class="ws65">epler family<span class="_ _2"></span><span class="ls2b">.N<span class="_ _1e"></span><span class="ls1">ot supported on Quadro and T<span class="_ _2"></span>esla C-class products.</span></span></span></div><div class="t m0 x2 h2 y67 ff1 fs0 fc0 sc0 ls1 ws65">LO<span class="_ _1"></span><span class="ws66">W_DP and ALL_ON are the only modes supported on GeF<span class="ws67">orce T<span class="_ _1"></span>itan de<span class="_ _1"></span><span class="ws68">vices. Requires<span class="_ _e"> </span>administrator</span></span></span></div><div class="t m0 x2 h4 y68 ff1 fs0 fc0 sc0 ls1 ws68">privile<span class="_ _1"></span><span class="ws69">ges. See<span class="_ _e"> </span><span class="ff3 ws6a">GPU Oper<span class="_ _1"></span>ation Mode<span class="_"> </span><span class="ff1">for more information about GOM.<span class="_ _13"> </span><span class="ws6b">GOM changes tak<span class="ls2c">ee<span class="_ _19"></span><span class="ls7">ff<span class="_ _0"></span><span class="ls1">ect after</span></span></span></span></span></span></span></div><div class="t m0 x2 h2 y69 ff1 fs0 fc0 sc0 ls1 ws6c">reboot. The<span class="_ _1f"> </span><span class="ws6d">reboot requirement might be remo<span class="ls3">ve<span class="ls2d">di<span class="_ _20"></span>nt<span class="_ _20"></span><span class="ls1">he future.<span class="_ _21"> </span><span class="ws6e">Compute only GOMs don’<span class="ls2e">ts<span class="_ _20"></span><span class="ls1">upport</span></span></span></span></span></span></span></div><div class="t m0 x2 h2 y6a ff1 fs0 fc0 sc0 ls1 ws0">WDDM (W<span class="_ _1"></span>indo<span class="_ _1"></span>ws Display Dri<span class="ls3">ve<span class="ls9">rM<span class="_ _5"></span><span class="ls1">odel)</span></span></span></div><div class="t m0 x3 h5 y6b ff2 fs0 fc0 sc0 ls1 ws0">−r<span class="_ _2"></span><span class="ls9">,−<span class="_ _5"></span><span class="ls1">−gpu−reset</span></span></div><div class="t m0 x2 h2 y6c ff1 fs0 fc0 sc0 ls2f ws0">Tr<span class="_ _0"></span><span class="ls1 ws6f">igger a reset of one or more GPUs.<span class="_ _c"> </span><span class="ws70">Can be used to clear GPU HW and SW state in situations that would</span></span></div><div class="t m0 x2 h4 y6d ff1 fs0 fc0 sc0 ls1 ws71">otherwise require a machine reboot.<span class="_ _3"> </span><span class="ls30">Ty<span class="_ _1c"></span></span>pically useful if a double bit ECC error has occurred.<span class="_ _13"> </span>Optional<span class="_"> </span><span class="ff3">−i</span></div><div class="t m0 x2 h2 y6e ff1 fs0 fc0 sc0 ls1 ws72">switch can be used to target one or more speciﬁc de<span class="_ _1"></span><span class="ws73">vices. W<span class="_ _1"></span><span class="ws72">ithout this option, all GPUs are reset.</span></span></div><div class="t m0 x2 h2 y6f ff1 fs0 fc0 sc0 ls1 ws74">Requires root.<span class="_ _3"> </span>There can't be an<span class="ls31">ya<span class="_ _d"></span><span class="ls1">pplications using these devices (e.g. CUD<span class="_ _2"></span><span class="ls31">Aa<span class="_ _5"></span><span class="ls1">pplication, graphics appli-</span></span></span></span></div><div class="t m0 x2 h2 y70 ff1 fs0 fc0 sc0 ls1 ws75">cation lik<span class="ls32">eXs<span class="_ _5"></span><span class="ls1">erver<span class="_ _1"></span><span class="ls32">,m<span class="_ _5"></span><span class="ls1">onitoring application lik<span class="ls32">eo<span class="_ _d"></span><span class="ls1">ther instance of n<span class="ws76">vidia-smi). There<span class="_ _17"> </span><span class="ws77">also can't be an<span class="ls33">yc<span class="_ _5"></span><span class="ls1">om-</span></span></span></span></span></span></span></span></span></span></div><div class="t m0 x2 h2 y71 ff1 fs0 fc0 sc0 ls1 ws0">pute applications running on an<span class="ls9">yo<span class="_ _5"></span><span class="ls1">ther GPU in the system.</span></span></div><div class="t m0 x2 h2 y72 ff1 fs0 fc0 sc0 ls1 ws78">When resetting GPUs that ha<span class="ls3 ws79">ve a<span class="ls1">cti<span class="_ _1"></span><span class="ls3">ve N<span class="_ _0"></span><span class="ls1 ws78">VLink connections to other GPUs, all GPUs with acti<span class="_ _1"></span><span class="ls3 ws79">ve N<span class="ls1">VLink</span></span></span></span></span></span></div><div class="t m0 x2 h4 y73 ff1 fs0 fc0 sc0 ls1 ws7a">connections must be reset together<span class="_ _1"></span><span class="ls34">,e<span class="_ _9"></span><span class="ls1">ither by omitting the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span><span class="ws7b">switch or using the<span class="_"> </span><span class="ff3">−i<span class="_"> </span></span>switch to specify all</span></span></span></div><div class="t m0 x2 h2 y19 ff1 fs0 fc0 sc0 ls1 ws0">GPUs with acti<span class="ls3 ws35">ve N</span>VLink connections.</div><div class="t m0 x2 h2 y1b ff1 fs0 fc0 sc0 ls1 ws7c">GPU reset is not guaranteed to work in all cases. It is not recommended for production en<span class="_ _1"></span><span class="ws7d">vironments at this</span></div><div class="t m0 x2 h2 y57 ff1 fs0 fc0 sc0 ls1 ws7e">time. In<span class="_ _e"> </span><span class="ws7f">some situations there may be HW components on the board that fail to re<span class="_ _1"></span><span class="ls3">ve<span class="_ _0"></span><span class="ls1">rt back to an initial</span></span></span></div><div class="t m0 x2 h2 y58 ff1 fs0 fc0 sc0 ls1 ws80">state following the reset request.<span class="_ _3"> </span><span class="ws81">This is more likely to be seen on Fermi-generation products vs. Kepler<span class="_ _1"></span>,</span></div><div class="t m0 x2 h2 y59 ff1 fs0 fc0 sc0 ls1 ws0">and more likely to be seen if the reset is being performed on a hung GPU.</div><div class="t m0 x2 h2 y74 ff1 fs0 fc0 sc0 ls3 ws0">Fo<span class="ls1">llo<span class="ws82">wing a reset, it is recommended that the health of each reset GPU be veriﬁed before further use.<span class="_ _c"> </span>The</span></span></div><div class="t m0 x2 h2 y40 ff1 fs0 fc0 sc0 ls0 ws82">nv<span class="_ _0"></span><span class="ls1 ws83">idia-healthmon tool is a good choice for this test.<span class="_ _3"> </span>If an<span class="ls35">yG<span class="_ _d"></span><span class="ls1">PU is not health<span class="ls35">yac<span class="_ _d"></span><span class="ls1">omplete reset should be</span></span></span></span></span></div><div class="t m0 x2 h2 y41 ff1 fs0 fc0 sc0 ls1 ws0">instigated by po<span class="_ _1"></span>wer cycling the node.</div><div class="t m0 x2 h4 y75 ff1 fs0 fc0 sc0 ls36 ws0">Vi<span class="_ _0"></span><span class="ls1">sit<span class="_"> </span><span class="ff3">http://developer<span class="_ _6"></span>.nvidia.com/gpu-deployment-kit<span class="_"> </span><span class="ff1">to do<span class="_ _1"></span>wnload the GDK and n<span class="_ _1"></span>vidia-healthmon.</span></span></span></div><div class="t m0 x3 h5 y76 ff2 fs0 fc0 sc0 ls1 ws0">−ac, −−applications−clocks=MEM_CLOCK,GRAPHICS_CLOCK</div><div class="t m0 x2 h2 y77 ff1 fs0 fc0 sc0 ls1 ws84">Speciﬁes maximum <memory<span class="_ _2"></span>,graphics> clocks as a pair (e.g. 2000,800) that deﬁnes GPU’<span class="_ _1"></span><span class="ls37">ss<span class="_ _9"></span><span class="ls1 ws85">peed while</span></span></div><div class="t m0 x2 h2 y78 ff1 fs0 fc0 sc0 ls1 ws86">running applications on a GPU.<span class="_ _8"> </span>Supported on Maxwell-based GeForce and from the K<span class="ws87">epler+ f<span class="_ _1"></span>amily in</span></div><div class="t m0 x2 h2 y79 ff1 fs0 fc0 sc0 ls38 ws87">Te<span class="_ _1b"></span><span class="ls1 ws0">sla/Quadro/T<span class="_ _1"></span>itan de<span class="ws34">vices. Requires<span class="_ _17"> </span></span>root unless restrictions are relaxed with the −acp command..</span></div><div class="t m0 x3 h5 y7a ff2 fs0 fc0 sc0 ls1 ws0">−rac, −−reset−applications−clocks</div><div class="t m0 x2 h2 y7b ff1 fs0 fc0 sc0 ls1 ws88">Resets the applications clocks to the default v<span class="_ _1"></span><span class="ws89">alue. Supported<span class="_ _12"> </span><span class="ws88">on Maxwell-based GeForce and from the</span></span></div><div class="t m0 x2 h2 y7c ff1 fs0 fc0 sc0 ls7 ws88">Ke<span class="_ _0"></span><span class="ls1 ws8a">pler+ family in T<span class="_ _2"></span>esla/Quadro/T<span class="_ _1"></span>itan de<span class="_ _1"></span><span class="ws8b">vices. Requires<span class="_ _e"> </span><span class="ws8c">root unless restrictions are relax<span class="_ _1"></span>ed with the −acp</span></span></span></div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 ls0 ws8c">nv<span class="_ _0"></span><span class="ls1 ws0">idia−smi 387.12<span class="_ _f"> </span><span class="ws21">2017/10/3 4</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89659514/bg5.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1 ws1">idia−smi(1) NVIDIA n<span class="_ _1"></span>vidia−smi(1)</span></div><div class="t m0 x2 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">command.</div><div class="t m0 x3 h5 y7d ff2 fs0 fc0 sc0 ls1 ws0">−acp, −−applications−clocks−permission=MODE</div><div class="t m0 x2 h2 y45 ff1 fs0 fc0 sc0 ls30 ws0">To<span class="_ _1b"></span><span class="ls1 ws8d">ggle whether applications clocks can be changed by all users or only by root.<span class="_ _13"> </span><span class="ls21 ws47">Av a<span class="_ _1b"></span></span><span class="ws8e">ilable arguments are</span></span></div><div class="t m0 x2 h2 y4 ff1 fs0 fc0 sc0 ls1 ws8f">0|UNRESTRICTED, 1|RESTRICTED.<span class="_ _3"> </span>Supported on Maxwell-based GeForce and from the Kepler+ f<span class="_ _1"></span>am-</div><div class="t m0 x2 h2 y5 ff1 fs0 fc0 sc0 ls1 ws0">ily in T<span class="_ _2"></span>esla/Quadro/Titan de<span class="_ _1"></span><span class="ws34">vices. Requires<span class="_ _17"> </span>root.</span></div><div class="t m0 x3 h5 y7e ff2 fs0 fc0 sc0 ls1 ws0">−pl, −−power−limit=PO<span class="_ _2"></span>WER_LIMIT</div><div class="t m0 x2 h2 y6 ff1 fs0 fc0 sc0 ls1 ws90">Speciﬁes maximum po<span class="_ _1"></span>wer limit in w<span class="ws91">atts. Accepts<span class="_ _1a"> </span>inte<span class="ws92">ger and ﬂoating point numbers.<span class="_ _13"> </span>Only on supported</span></span></div><div class="t m0 x2 h2 y7 ff1 fs0 fc0 sc0 ls1 ws92">de<span class="_ _1"></span><span class="ws93">vices from Kepler family<span class="_ _2"></span><span class="ls39">.R<span class="_ _14"></span><span class="ls1">equires administrator privile<span class="ws94">ges. V<span class="_ _6"></span><span class="ws95">alue needs to be between Min and Max</span></span></span></span></span></div><div class="t m0 x2 h2 y8 ff1 fs0 fc0 sc0 ls1 ws0">Power Limit as reported by n<span class="_ _2"></span>vidia-smi.</div><div class="t m0 x3 h5 y2f ff2 fs0 fc0 sc0 ls1 ws0">−am, −−accounting−mode=MODE</div><div class="t m0 x2 h2 y7f ff1 fs0 fc0 sc0 ls1 ws96">Enables or disables GPU Accounting.<span class="_ _8"> </span><span class="ls0">Wi<span class="_ _0"></span></span>th GPU Accounting one can k<span class="ws97">eep track of usage of resources</span></div><div class="t m0 x2 h2 y80 ff1 fs0 fc0 sc0 ls1 ws98">throughout lifespan of a single process.<span class="_ _3"> </span><span class="ws99">Only on supported de<span class="_ _1"></span>vices from Kepler f<span class="_ _1"></span>amily<span class="_ _1"></span><span class="ls3a">.R<span class="_ _4"></span><span class="ls1">equires adminis-</span></span></span></div><div class="t m0 x2 h2 yd ff1 fs0 fc0 sc0 ls1 ws0">trator pri<span class="_ _1"></span>vile<span class="ws34">ges. A<span class="_ _2"></span><span class="ls7">va<span class="_ _0"></span><span class="ls1 ws0">ilable arguments are 0|DISABLED or 1|EN<span class="_ _1"></span>ABLED.</span></span></span></div><div class="t m0 x3 h5 y33 ff2 fs0 fc0 sc0 ls1 ws0">−caa, −−clear−accounted−apps</div><div class="t m0 x2 h2 y10 ff1 fs0 fc0 sc0 ls1 ws9a">Clears all processes accounted so far<span class="_ _2"></span><span class="ls3b">.O<span class="_ _10"></span><span class="ls1">nly on supported de<span class="ws9b">vices from K<span class="_ _1"></span>epler family<span class="_ _2"></span><span class="ls3c">.R<span class="_ _10"></span><span class="ls1">equires administra-</span></span></span></span></span></div><div class="t m0 x2 h2 y11 ff1 fs0 fc0 sc0 ls1 ws0">tor pri<span class="_ _1"></span>vileges.</div><div class="t m0 x4 h5 y13 ff2 fs0 fc0 sc0 ls1 ws0">−−auto−boost−default=MODE</div><div class="t m0 x2 h2 y34 ff1 fs0 fc0 sc0 ls1 ws9c">Set the default auto boost polic<span class="_ _1"></span><span class="ls3d">yt<span class="_ _5"></span>o0<span class="_ _d"></span><span class="ls1">/DISABLED or 1/EN<span class="ws9d">ABLED, enforcing the change only after the last</span></span></span></div><div class="t m0 x2 h2 y35 ff1 fs0 fc0 sc0 ls1 ws9e">boost client has e<span class="ws9f">xited. Only<span class="_ _c"> </span></span>on certain T<span class="_ _2"></span>esla devices from the K<span class="_ _1"></span>epler+ f<span class="wsa0">amily and Maxwell-based</span></div><div class="t m0 x2 h2 y36 ff1 fs0 fc0 sc0 ls1 ws0">GeForce de<span class="_ _1"></span><span class="ws34">vices. Requires<span class="_ _17"> </span>root.</span></div><div class="t m0 x4 h5 y81 ff2 fs0 fc0 sc0 ls1 ws34">−−auto−boost−default−for<span class="_ _1"></span>ce=MODE</div><div class="t m0 x2 h2 y82 ff1 fs0 fc0 sc0 ls1 wsa1">Set the default auto boost polic<span class="ls3e">yt<span class="_ _20"></span>o0<span class="_ _a"></span><span class="ls1">/DISABLED or 1/EN<span class="_ _1"></span><span class="wsa2">ABLED, enforcing the change immediately<span class="_ _2"></span>.</span></span></span></div><div class="t m0 x2 h2 y83 ff1 fs0 fc0 sc0 ls1 wsa3">Only on certain T<span class="_ _2"></span>esla devices from the K<span class="_ _1"></span>epler+ family and Maxwell-based GeF<span class="wsa4">orce de<span class="_ _1"></span><span class="wsa5">vices. Requires</span></span></div><div class="t m0 x2 h2 y3a ff1 fs0 fc0 sc0 ls1 wsa5">root.</div><div class="t m0 x4 h5 y84 ff2 fs0 fc0 sc0 ls1 wsa5">−−auto−boost−permission=MODE</div><div class="t m0 x2 h2 y3c ff1 fs0 fc0 sc0 ls1 wsa5">Allo<span class="ls3f">wn<span class="_ _14"></span><span class="ls1 wsa6">on-admin/root control o<span class="ls3">ve<span class="ls3f">ra<span class="_ _4"></span><span class="ls1">uto boost mode.<span class="_ _22"> </span><span class="ls21 ws47">Av a<span class="_"> </span></span>ilable arguments are 0|UNRESTRICTED,</span></span></span></span></span></div><div class="t m0 x2 h2 y3d ff1 fs0 fc0 sc0 ls1 wsa7">1|RESTRICTED. Only<span class="_ _23"> </span><span class="wsa8">on certain T<span class="_ _2"></span>esla devices from the K<span class="_ _1"></span>epler+ family and Maxwell-based GeForce</span></div><div class="t m0 x2 h2 y3e ff1 fs0 fc0 sc0 ls1 wsa8">de<span class="_ _1"></span><span class="ws34">vices. Requires<span class="_ _1d"> </span>root.</span></div><div class="t m0 x3 h5 y74 ff2 fs0 fc0 sc0 ls1 ws0">[plus optional]</div><div class="t m0 x3 h5 y40 ff2 fs0 fc0 sc0 ls1 ws0">−i, −−id=ID</div><div class="t m0 x2 h2 y41 ff1 fs0 fc0 sc0 ls1 wsa9">Modify a single speciﬁed GPU.<span class="_ _3"> </span>The speciﬁed id may be the GPU/Unit's 0−based inde<span class="ls40">xi<span class="_ _d"></span><span class="ls41">nt<span class="_ _d"></span><span class="ls1 wsaa">he natural enu-</span></span></span></div><div class="t m0 x2 h2 y85 ff1 fs0 fc0 sc0 ls1 wsab">meration returned by the dri<span class="ls3">ve<span class="ls0 wsac">r, t<span class="_ _0"></span></span></span><span class="wsad">he GPU's board serial number<span class="_ _1"></span><span class="ls42">,t<span class="_ _d"></span><span class="ls1">he GPU's UUID, or the GPU's PCI bus ID</span></span></span></div><div class="t m0 x2 h2 y75 ff1 fs0 fc0 sc0 ls1 wsae">(as domain:bus:de<span class="_ _1"></span>vice.function in he<span class="wsaf">x). It<span class="_ _17"> </span><span class="wsb0">is recommended that users desiring consistenc<span class="ls43">yu<span class="_ _5"></span><span class="ls1">se either UUID</span></span></span></span></div><div class="t m0 x2 h2 y86 ff1 fs0 fc0 sc0 ls1 wsb1">or PCI bus ID, since de<span class="_ _1"></span>vice enumeration ordering is not guaranteed to be consistent between reboots and</div><div class="t m0 x2 h2 y87 ff1 fs0 fc0 sc0 ls1 ws0">board serial number might be shared between multiple GPUs on the same board.</div><div class="t m0 x3 h5 y79 ff2 fs0 fc0 sc0 ls1 ws0">UNIT MODIFICA<span class="_ _2"></span>TION OPTIONS</div><div class="t m0 x3 h5 y88 ff2 fs0 fc0 sc0 ls1 ws0">−t, −−toggle−led=ST<span class="_ _2"></span><span class="ls44">AT<span class="_ _1b"></span><span class="ls1">E</span></span></div><div class="t m0 x2 h4 y89 ff1 fs0 fc0 sc0 ls1 wsb2">Set the LED indicator state on the front and back of the unit to the speciﬁed color<span class="_ _1"></span><span class="ls45">.S<span class="_ _24"></span><span class="ls1 wsb3">ee the (<span class="ff3">UNIT</span></span></span></div><div class="t m0 x2 h4 y8a ff3 fs0 fc0 sc0 lsc wsb3">AT<span class="_ _0"></span><span class="ls1">TRIBUTES<span class="ff1 ls46">)s<span class="_ _19"></span><span class="ls1 wsb4">ection for a description of the LED states.<span class="_ _13"> </span>Allowed colors are 0|GREEN and 1|AMBER.</span></span></span></div><div class="t m0 x2 h2 y8b ff1 fs0 fc0 sc0 ls1 ws0">Requires root.</div><div class="t m0 x1 h2 y2b ff1 fs0 fc0 sc0 ls0 ws0">nv<span class="_ _0"></span><span class="ls1">idia−smi 387.12<span class="_ _f"> </span><span class="ws21">2017/10/3 5</span></span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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