ppt高效制作技巧与方法

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ppt高效制作技巧与方法
<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/2/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">www.lattic<span class="_ _0"></span>esemi.com<span class="_ _1"> </span><span class="ff2 ls1">1<span class="_ _2"> </span><span class="fs1 ls2">rd1174_01.1</span></span></div><div class="t m0 x1 h3 y2 ff1 fs1 fc0 sc0 ls3 ws1">March 2014<span class="_ _3"> </span><span class="ls2 ws2">Reference Design RD1174</span></div><div class="t m0 x1 h4 y3 ff2 fs2 fc0 sc0 ls4 ws3">© 2014 Latti<span class="_ _4"></span>ce Semiconductor<span class="_ _4"></span> Corp. All La<span class="_ _4"></span>ttice trade<span class="_ _4"></span>marks, register<span class="_ _4"></span>ed trademarks<span class="_ _4"></span>, patents<span class="_ _4"></span>, and disclai<span class="_ _4"></span>mers are as list<span class="_ _4"></span>ed at www<span class="_ _5"></span><span class="ls5 ws4">.latticese<span class="_ _4"></span>mi.com/legal.<span class="_ _4"></span> All other brand<span class="_ _4"></span> </span></div><div class="t m0 x1 h4 y4 ff2 fs2 fc0 sc0 ls6 ws5">or product name<span class="_ _4"></span>s are trademarks or registe<span class="_ _4"></span>red trademarks of their r<span class="_ _4"></span>espectiv<span class="_ _4"></span>e holders<span class="_ _4"></span>. The specifications and in<span class="_ _4"></span>formation here<span class="_ _4"></span>in<span class="ls7 ws6"> are subject to cha<span class="_ _4"></span>nge without notice<span class="_ _5"></span>.</span></div><div class="t m0 x1 h5 y5 ff1 fs3 fc0 sc0 ls8 ws0">Intr<span class="_ _4"></span>oduction </div><div class="t m0 x1 h2 y6 ff2 fs0 fc0 sc0 ls9 ws7">The Synchronous dyna<span class="_ _4"></span>mic random access mem<span class="_ _4"></span>or<span class="_ _0"></span>y (SDRAM)<span class="ws8"> is dynamic random acce<span class="_ _4"></span>ss memor<span class="_ _0"></span>y (DRAM) that </span></div><div class="t m0 x1 h2 y7 ff2 fs0 fc0 sc0 lsa ws9">has a synchronous interf<span class="_ _5"></span>ace. SDR (Single Data Rate) SDRAM ca<span class="_ _4"></span>n accept one command and tr<span class="_ _4"></span>ansf<span class="_ _5"></span>er one word of </div><div class="t m0 x1 h2 y8 ff2 fs0 fc0 sc0 lsb wsa">data per cloc<span class="_ _4"></span>k cycle. T<span class="_ _6"></span>ypical SDR SDRAM cloc<span class="_ _4"></span>k rates are 6<span class="_ _4"></span>6, 100, and 133 MHz (p<span class="_ _4"></span>eriods of 15, 10, and 7.5 ns). I<span class="_ _4"></span>t </div><div class="t m0 x1 h2 y9 ff2 fs0 fc0 sc0 lsc wsb">is a mainstream memo<span class="_ _4"></span>r<span class="_ _0"></span>y of choice due to speed, b<span class="_ _5"></span>urst access and pipeline f<span class="_ _5"></span>eatures. </div><div class="t m0 x1 h2 ya ff2 fs0 fc0 sc0 lsd wsc">This SDRAM Controller ref<span class="_ _5"></span>erence design, located betw<span class="_ _4"></span>een the SDRAM and t<span class="_ _4"></span>he bus m<span class="_ _4"></span>aster<span class="_ _5"></span>, reduces the user’<span class="_ _5"></span>s </div><div class="t m0 x1 h2 yb ff2 fs0 fc0 sc0 lse wsd">eff<span class="_ _4"></span>or<span class="_ _0"></span>t to deal with the SDRAM command <span class="lsf wse">interface b<span class="_ _5"></span>y providing a <span class="ls10 wsf">simple generic system inte<span class="_ _0"></span><span class="ls11 ws10">rf<span class="_ _4"></span>ace to the bus master<span class="_ _5"></span>. </span></span></span></div><div class="t m0 x1 h2 yc ff2 fs0 fc0 sc0 lsd ws11">The design is impleme<span class="_ _4"></span>nted in V<span class="_ _7"></span>erilog language. Th<span class="_ _4"></span>e Lattice Diamond</div><div class="t m0 x2 h6 yd ff1 fs4 fc0 sc0 ls1 ws0">®</div><div class="t m0 x3 h2 ye ff2 fs0 fc0 sc0 lse ws12"> f<span class="_ _4"></span>or MachXO3L de<span class="_ _4"></span>vice and Lattice </div><div class="t m0 x1 h2 yf ff2 fs0 fc0 sc0 ls12 ws13">iCEcube2™ f<span class="_ _5"></span>or iCE40™ device<span class="_ _4"></span> Place and Route <span class="_ _4"></span>to<span class="ls13 ws14">ol integr<span class="_ _5"></span>ated with the Synopsys Synplify Pro</span></div><div class="t m0 x4 h6 y10 ff1 fs4 fc0 sc0 ls1 ws0">®</div><div class="t m0 x5 h2 y11 ff2 fs0 fc0 sc0 lsa ws15"> synthesis tool are </div><div class="t m0 x1 h2 y12 ff2 fs0 fc0 sc0 ls14 ws16">used f<span class="_ _5"></span>or the implementation of t<span class="_ _4"></span>he design. The<span class="_ _4"></span> design can be target<span class="_ _4"></span>ed to other iCE4<span class="_ _4"></span>0 FPGA product f<span class="_ _5"></span>amily </div><div class="t m0 x1 h2 y13 ff2 fs0 fc0 sc0 ls15 ws0">de<span class="_ _4"></span>vices.</div><div class="t m0 x1 h5 y14 ff1 fs3 fc0 sc0 ls16 ws0">Features </div><div class="t m0 x1 h2 y15 ff2 fs0 fc0 sc0 ls17 ws17">•<span class="_ _8"> </span>Suppor<span class="_ _9"></span>ts up to 27<span class="_ _0"></span> addres<span class="_ _0"></span>s space, up to <span class="_ _0"></span>4 banks </div><div class="t m0 x1 h2 y16 ff2 fs0 fc0 sc0 ls18 ws18">•<span class="_ _8"> </span>Compile tim<span class="_ _0"></span>e configurable timing parameters<span class="_ _0"></span> like (CAS latency<span class="_ _7"></span>, tRP<span class="_ _a"></span>, tRCD<span class="_ _5"></span>, tREFC, tMRD …) </div><div class="t m0 x1 h2 y17 ff2 fs0 fc0 sc0 lsa ws19">•<span class="_ _8"> </span>Simplifies SDRAM command in<span class="_ _4"></span>terf<span class="_ _5"></span>ace to standard system read/write interf<span class="_ _5"></span>ace </div><div class="t m0 x1 h2 y18 ff2 fs0 fc0 sc0 ls19 ws1a">•<span class="_ _8"> </span>Suppor<span class="_ _9"></span>ts Auto Refresh and Self<span class="_ _0"></span> Refresh </div><div class="t m0 x1 h2 y19 ff2 fs0 fc0 sc0 lsa ws19">•<span class="_ _8"> </span>Suppor<span class="_ _0"></span>ts fle<span class="_ _5"></span>xible Row and<span class="_ _4"></span> Column addressing </div><div class="t m0 x1 h2 y1a ff2 fs0 fc0 sc0 ls1a ws1b">•<span class="_ _8"> </span>Suppor<span class="_ _9"></span>ts CAS latencies of 2 and<span class="_ _0"></span> 3 </div><div class="t m0 x1 h2 y1b ff2 fs0 fc0 sc0 ls1a ws1c">•<span class="_ _8"> </span>Run time c<span class="_ _0"></span>onfigurable Refresh rate </div><div class="t m0 x1 h2 y1c ff2 fs0 fc0 sc0 ls1b ws1d">•<span class="_ _8"> </span>A<span class="_ _4"></span>utomatically gener<span class="_ _4"></span>ates initialization and ref<span class="_ _4"></span>resh sequences </div><div class="t m0 x1 h2 y1d ff2 fs0 fc0 sc0 lsd ws1e">•<span class="_ _8"> </span>Fle<span class="_ _4"></span>xib<span class="_ _4"></span>le user controlled b<span class="_ _5"></span>urst length of 1, 2, 4, 8 and page as well as sto<span class="_ _4"></span>p signal </div><div class="t m0 x1 h2 y1e ff2 fs0 fc0 sc0 lsb ws1f">•<span class="_ _8"> </span>User friendly control and status signals lik<span class="_ _5"></span>e busy<span class="_ _7"></span>, command ac<span class="_ _5"></span>knowledge, data v<span class="_ _5"></span>alid and request, indications f<span class="_ _5"></span>or </div><div class="t m0 x6 h2 y1f ff2 fs0 fc0 sc0 ls1c ws20">completion of write and re<span class="_ _4"></span>ad data </div><div class="t m0 x1 h2 y20 ff2 fs0 fc0 sc0 ls9 ws21">•<span class="_ _8"> </span>User controlled o<span class="_ _4"></span>peration modes b<span class="_ _5"></span>y configuring load mode register </div><div class="t m0 x1 h2 y21 ff2 fs0 fc0 sc0 ls1d ws22">•<span class="_ _8"> </span>Provision for disable auto refresh<span class="_ _0"></span> </div><div class="t m0 x1 h2 y22 ff2 fs0 fc0 sc0 ls14 ws23">•<span class="_ _8"> </span>P<span class="_ _5"></span>ower<span class="_ _4"></span> down mode </div><div class="t m0 x7 h7 y23 ff1 fs5 fc0 sc0 ls1e ws24">SDR SDRAM Contr<span class="_ _4"></span>oller </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/bg2.jpg"><div class="t m0 x8 h2 y1 ff2 fs0 fc0 sc0 ls1 ws0">2</div><div class="t m0 x9 h8 y24 ff1 fs6 fc0 sc0 ls1f ws25">SDR SDRAM Controller </div><div class="t m0 x1 h5 y25 ff1 fs3 fc0 sc0 ls20 ws26">System Bloc<span class="_ _5"></span>k Diagram</div><div class="t m0 x1 h2 y26 ff3 fs0 fc0 sc0 ls21 ws27">Figure 1. Syst<span class="_ _4"></span>em Bloc<span class="_ _4"></span>k Diagram</div><div class="t m0 x1 h5 y27 ff1 fs3 fc0 sc0 ls22 ws28">Functional Description</div><div class="t m0 x1 h2 y28 ff3 fs0 fc0 sc0 ls23 ws29">Figure 2. Functional Bloc<span class="_ _4"></span>k Diagram</div><div class="c xa y29 w2 h9"><div class="t m0 xb ha y2a ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y2b ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y2c ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y2d ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y2e ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y2f ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y30 ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div><div class="t m0 xb ha y31 ff2 fs7 fc1 sc0 ls1 ws0"><span class="fc2 sc0"> </span></div></div><div class="t m0 xc ha y32 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y33 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y34 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y35 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y36 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y37 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xc ha y38 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xd ha y39 ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xd ha y3a ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xd ha y3b ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xd ha y3c ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="t m0 xd ha y3d ff2 fs7 fc1 sc0 ls24 ws0">IOB<span class="_ _b"></span><span class="ls1"> </span></div><div class="c xa y29 w2 h9"><div class="t m0 xe ha y3e ff1 fs7 fc1 sc0 ls25 ws2a">SDR SDRAM </div><div class="t m0 xe ha y3f ff1 fs7 fc1 sc0 ls25 ws0">Controller<span class="_ _c"></span><span class="ff2 ls1"> </span></div><div class="t m0 xf ha y40 ff1 fs7 fc1 sc0 ls26 ws0">Processor</div></div><div class="t m0 x10 ha y41 ff2 fs7 fc1 sc0 ls1 ws0"> </div><div class="t m0 x11 hb y42 ff2 fs8 fc1 sc0 ls27 ws0">i_clk<span class="_ _7"></span> </div><div class="t m0 x11 hb y43 ff2 fs8 fc1 sc0 ls28 ws0">i_rst<span class="_ _5"></span> </div><div class="c xa y29 w2 h9"><div class="t m0 x12 hc y44 ff2 fs9 fc1 sc0 ls29 ws0">CONTROL</div></div><div class="t m0 x13 hb y45 ff2 fs8 fc1 sc0 ls1 ws0"> </div><div class="t m0 x11 hb y46 ff2 fs9 fc1 sc0 ls1 ws0">STATUS<span class="_ _d"></span><span class="fs8"> </span></div><div class="c xa y29 w2 h9"><div class="t m0 x14 hc y47 ff2 fs9 fc1 sc0 ls2a ws0">ADDRESS</div></div><div class="t m0 x15 hb y48 ff2 fs8 fc1 sc0 ls1 ws0"> </div><div class="t m0 x16 hb y49 ff2 fs8 fc1 sc0 ls1 ws0">i_data<span class="_ _6"></span> </div><div class="t m0 x17 hb y4a ff2 fs8 fc1 sc0 ls2b ws0">o_data<span class="_ _a"></span> </div><div class="c xa y29 w2 h9"><div class="t m0 x7 ha y4b ff1 fs7 fc1 sc0 ls1 ws2b">SDR SD </div><div class="t m0 x7 ha y4c ff1 fs7 fc1 sc0 ls2c ws0">Memory </div><div class="t m0 x7 ha y4d ff1 fs7 fc1 sc0 ls2c ws0">Device</div><div class="t m0 x18 ha y4e ff2 fs7 fc1 sc0 ls1 ws0"> </div></div><div class="t m0 x19 hd y4f ff2 fsa fc1 sc0 ls2d ws0">o_sdram_clk<span class="_ _d"></span><span class="ls1"> </span></div><div class="t m0 x19 hb y50 ff2 fs9 fc1 sc0 ls2e ws0">COMMAND<span class="_ _0"></span><span class="fs8 ls1"> </span></div><div class="t m0 x19 hb y51 ff2 fs9 fc1 sc0 ls29 ws0">ADDRESS<span class="_ _e"></span><span class="fs8 ls1"> </span></div><div class="t m0 x19 hd y52 ff2 fsa fc1 sc0 ls2f ws0">i_sdram_dat</div><div class="c x19 y53 w3 he"><div class="t m0 x1a hd y54 ff2 fsa fc1 sc0 ls1 ws0">a</div></div><div class="t m0 x1b hd y52 ff2 fsa fc1 sc0 ls1 ws0"> </div><div class="t m0 x1c hd y55 ff2 fsa fc1 sc0 ls1 ws0">o</div><div class="c xa y29 w2 h9"><div class="t m0 x1d hd y56 ff2 fsa fc1 sc0 ls2d ws0">_sdram_data</div></div><div class="t m0 x1e hd y55 ff2 fsa fc1 sc0 ls1 ws0"> </div><div class="t m0 x1f hf y57 ff2 fsb fc1 sc0 ls1 ws0">A<span class="ff4">u</span><span class="ls30">torefresh </span></div><div class="c x20 y58 w4 h10"><div class="t m0 x21 hf y59 ff2 fsb fc1 sc0 ls31 ws0">Co<span class="ff4 ls1">u</span><span class="ls32">nter<span class="_ _b"></span><span class="ls1"> </span></span></div></div><div class="t m0 x1f hf y5a ff2 fsb fc1 sc0 ls31 ws0">100 <span class="ff4 ls1">u</span><span class="ls33 ws2c">s delay </span></div><div class="c x20 y58 w4 h10"><div class="t m0 x21 hf y5b ff2 fsb fc1 sc0 ls34 ws0">generator<span class="_ _b"></span> </div></div><div class="t m0 x22 h11 y5c ff2 fsc fc1 sc0 ls35 ws0">Initialization </div><div class="t m0 x22 h11 y5d ff2 fsc fc1 sc0 ls36 ws0">FSM<span class="_ _d"></span><span class="ls1"> </span></div><div class="t m0 x22 h11 y5e ff2 fsc fc1 sc0 ls37 ws0">Command </div><div class="c x20 y58 w4 h10"><div class="t m0 x23 h11 y5f ff2 fsc fc1 sc0 ls37 ws0">Generation </div></div><div class="t m0 x22 h11 y60 ff2 fsc fc1 sc0 ls36 ws0">FSM<span class="_ _d"></span><span class="ls1"> </span></div><div class="t m0 x22 h11 y61 ff2 fsc fc1 sc0 ls38 ws0">Stat<span class="ff4 ls1">u</span><span class="ls39">s </span></div><div class="c x20 y58 w4 h10"><div class="t m0 x23 h11 y62 ff2 fsc fc1 sc0 ls3a ws0">Signals </div></div><div class="c x24 y63 w5 h12"><div class="t m0 x25 h11 y64 ff2 fsc fc1 sc0 ls3b ws0">Generation</div></div><div class="t m0 x26 h13 y65 ff2 fsd fc1 sc0 ls3c ws0">Control </div><div class="c x20 y58 w4 h10"><div class="t m0 x16 h13 y66 ff2 fsd fc1 sc0 ls3d ws0">Logic </div><div class="t m0 x16 h13 y67 ff2 fsd fc1 sc0 ls3c ws0">Mod<span class="ff4 ls1">u</span><span class="ls3e">le<span class="_ _7"></span> </span></div><div class="t m0 x27 hf y68 ff2 fsb fc1 sc0 ls32 ws2d">SDR SDRAM </div><div class="t m0 x28 hf y69 ff2 fsb fc1 sc0 ls1 ws0"> </div></div><div class="t m0 x29 h14 y6a ff2 fse fc1 sc0 ls3f ws0">i_clk<span class="_ _f"> </span> </div><div class="t m0 x29 h14 y6b ff2 fse fc1 sc0 ls40 ws0">i_rst<span class="_ _10"> </span> </div><div class="t m0 x2a h14 y6c ff2 fse fc1 sc0 ls41 ws0">CONTROL<span class="_ _11"> </span> </div><div class="t m0 x29 h14 y6d ff2 fse fc1 sc0 ls1 ws0">STATUS<span class="_ _0"></span> </div><div class="t m0 x2a h14 y6e ff2 fse fc1 sc0 ls41 ws0">ADDRESS </div><div class="t m0 x2b h14 y6f ff2 fse fc1 sc0 ls1 ws0">i_data<span class="_ _12"> </span> </div><div class="t m0 x2a h14 y70 ff2 fse fc1 sc0 ls42 ws0">o_data<span class="_ _13"> </span> </div><div class="t m0 x2c h14 y71 ff2 fse fc1 sc0 ls43 ws0">o_sdram_clk<span class="_"> </span> </div><div class="t m0 x2c h14 y72 ff2 fse fc1 sc0 ls40 ws0">COMMAND<span class="_ _14"> </span> </div><div class="t m0 x2c h14 y73 ff2 fse fc1 sc0 ls41 ws0">ADDRESS </div><div class="t m0 x2c h14 y74 ff2 fse fc1 sc0 ls44 ws0">i_sdram_data<span class="_"> </span> </div><div class="t m0 x2c h14 y75 ff2 fse fc1 sc0 ls1 ws0">o_sdra<span class="_ _0"></span>m_data<span class="_"> </span> </div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/bg3.jpg"><div class="t m0 x8 h2 y1 ff2 fs0 fc0 sc0 ls1 ws0">3</div><div class="t m0 x9 h8 y24 ff1 fs6 fc0 sc0 ls1f ws25">SDR SDRAM Controller </div><div class="t m0 x1 h5 y25 ff1 fs3 fc0 sc0 ls45 ws0">Design Details</div><div class="t m0 x1 h8 y76 ff1 fs6 fc0 sc0 ls46 ws0">Initialization</div><div class="t m0 x1 h2 y77 ff2 fs0 fc0 sc0 ls47 ws2e">Prior to perf<span class="_ _4"></span>orming nor<span class="_ _0"></span>mal SDRAM memor<span class="_ _0"></span>y access, memor<span class="_ _0"></span>y needs to be initializ<span class="_ _4"></span>ed by a seque<span class="_ _4"></span>nce of commands. </div><div class="t m0 x1 h2 y78 ff2 fs0 fc0 sc0 ls47 ws2f">Operationa<span class="_ _4"></span>l procedures other<span class="_ _4"></span> than those specified ma<span class="_ _5"></span>y result in unde<span class="_ _4"></span>fined oper<span class="_ _4"></span>ation. The Initia<span class="_ _4"></span>lization FSM han-</div><div class="t m0 x1 h2 y79 ff2 fs0 fc0 sc0 ls48 ws30">dles this initialization.</div><div class="t m0 x1 h2 y7a ff3 fs0 fc0 sc0 ls48 ws31">Figure 3. SDRAM Initialization flow chart</div><div class="t m0 x1 h8 y7b ff1 fs6 fc0 sc0 ls49 ws32">Command Generation</div><div class="t m0 x1 h2 y7c ff2 fs0 fc0 sc0 ls14 ws23">Commands are g<span class="_ _4"></span>enerated in<span class="_ _4"></span> command gener<span class="_ _4"></span>ation FSM.<span class="_ _4"></span> T<span class="_ _6"></span>able 1 sho<span class="_ _4"></span>ws T<span class="_ _6"></span>r<span class="_ _0"></span>uth tab<span class="_ _5"></span>le for v<span class="_ _5"></span>arious commands and <span class="_ _4"></span>cor-</div><div class="t m0 x1 h2 y7d ff2 fs0 fc0 sc0 ls4a ws33">responding SDR SDRAM control signal lev<span class="_ _5"></span>els.</div><div class="t m0 x1 h2 y7e ff3 fs0 fc0 sc0 ls4b ws34">T<span class="_ _7"></span>able 1. T<span class="_ _7"></span>ruth T<span class="_ _5"></span>able f<span class="_ _4"></span>or SDRAM Commands</div><div class="t m0 x1 h2 y7f ff2 fs0 fc0 sc0 ls47 ws35">Command genera<span class="_ _4"></span>tion FSM states and its contr<span class="_ _4"></span>ol signals are shown in Fig<span class="_ _4"></span>ure 4.</div><div class="t m0 x2d h3 y80 ff1 fs1 fc0 sc0 ls4c ws0">Commands<span class="_ _15"> </span>CS<span class="_ _16"> </span>RAS<span class="_ _17"> </span>CAS<span class="_ _18"> </span>WE</div><div class="t m0 x2e h3 y81 ff4 fs1 fc0 sc0 ls1 ws0">N<span class="ff2 ls4d ws36">o Opera<span class="_ _4"></span>tion (<span class="ff4 ls1 ws0">N<span class="ff2 ls4e">O<span class="_ _19"></span>P<span class="_ _19"></span>)<span class="_ _18"> </span>L<span class="_ _11"></span>HHH</span></span></span></div><div class="t m0 x2e h3 y82 ff2 fs1 fc0 sc0 ls4f ws0">Active<span class="_ _1a"> </span>L<span class="_ _1b"> </span>L<span class="_ _1c"> </span>H<span class="_ _1d"> </span>H</div><div class="t m0 x2e h3 y83 ff2 fs1 fc0 sc0 ls50 ws0">R<span class="_ _1e"></span>e<span class="_ _1e"></span>a<span class="_ _1e"></span>d<span class="_ _1f"> </span>LHLH</div><div class="t m0 x2e h3 y84 ff2 fs1 fc0 sc0 ls51 ws0">Write<span class="_ _20"> </span>L<span class="_ _1c"> </span>H<span class="_ _1c"> </span>L<span class="_ _1b"> </span>L</div><div class="t m0 x2e h3 y85 ff2 fs1 fc0 sc0 ls52 ws37">Burst T<span class="_ _6"></span>er<span class="_ _0"></span>minate<span class="_ _21"> </span>L<span class="_ _1c"> </span>H<span class="_ _1d"> </span>H<span class="_ _1c"> </span>L</div><div class="t m0 x2e h3 y86 ff2 fs1 fc0 sc0 ls53 ws0">Precharge<span class="_ _22"> </span>L<span class="_ _1b"> </span>L<span class="_ _1c"> </span>H<span class="_ _1c"> </span>L</div><div class="t m0 x2e h3 y87 ff2 fs1 fc0 sc0 ls54 ws38">Auto Refresh or <span class="_ _4"></span>Self Refresh<span class="_ _23"> </span>L<span class="_ _1b"> </span>L<span class="_ _1b"> </span>L<span class="_ _1c"> </span>H</div><div class="t m0 x2f h15 y88 ff2 fsf fc1 sc0 ls55 ws39"> <span class="_ _24"></span><span class="ls56 ws3a">IDLE STATE<span class="_ _25"></span><span class="ls1 ws0"> </span></span></div><div class="t m0 x30 h15 y89 ff4 fsf fc1 sc0 ls1 ws0">W<span class="ff2 ls57 ws3b">ait for 100 </span>u<span class="ff2 ls58">s </span></div><div class="t m0 x2f h15 y8a ff2 fsf fc1 sc0 ls59 ws0"> <span class="_ _d"></span><span class="ls5a ws3c">Precharge all the <span class="ff4 ls1 ws0">b<span class="ff2 ls5b">anks<span class="_ _7"></span> </span></span></span></div><div class="t m0 x2f h15 y8b ff2 fsf fc1 sc0 ls5c ws0"> <span class="_ _7"></span><span class="ff4 ls1">W<span class="ff2 ls5d ws3d">ait for Precharge Period<span class="_ _9"></span>-<span class="_ _11"> </span>tRP<span class="_ _b"></span> </span></span></div><div class="t m0 x2f h15 y8c ff2 fsf fc1 sc0 ls5e ws0">Iss<span class="ff4 ls1">u</span><span class="ls5f ws3e">e first A</span><span class="ff4 ls1">u</span><span class="ws3f">to Reresh Command<span class="_ _6"></span> </span></div><div class="t m0 x31 h15 y8d ff2 fsf fc1 sc0 ls1 ws0"> <span class="_ _4"></span><span class="ff4">W<span class="ff2 ls60 ws40">ait for A</span>u<span class="ff2 ls57 ws3f">to Refresh Period<span class="_ _26"> </span>-tRFC<span class="_ _d"></span><span class="ls1 ws0"> </span></span></span></div><div class="t m0 x32 h15 y8e ff2 fsf fc1 sc0 ls61 ws0">A </div><div class="t m0 x33 h15 y8f ff2 fsf fc1 sc0 ls62 ws41"> A </div><div class="t m0 x34 h15 y90 ff2 fsf fc1 sc0 ls5e ws0">Iss<span class="ff4 ls1">u</span><span class="ls63 ws42">e Second A</span><span class="ff4 ls1">u</span><span class="ls57 ws43">to Refresh Command<span class="_ _e"></span><span class="ls1 ws0"> </span></span></div><div class="t m0 x34 h15 y91 ff2 fsf fc1 sc0 ls64 ws39"> <span class="_ _6"></span><span class="ff4 ls1 ws0">W<span class="ff2 ls65 ws44">ait for A</span>u<span class="_"> </span><span class="ff2 ls66 ws45">to Refresh Period<span class="_ _26"> </span>-<span class="_ _11"> </span>tRFC<span class="_ _e"></span><span class="ls1 ws0"> </span></span></span></div><div class="t m0 x34 h15 y92 ff2 fsf fc1 sc0 ls67 ws0"> <span class="_ _7"></span> <span class="_ _27"> </span> <span class="_ _9"></span>Load Mode Register<span class="_ _a"></span> </div><div class="t m0 x35 h15 y93 ff4 fsf fc1 sc0 ls1 ws0">W<span class="ff2 ls56 ws46">ait for Load Mode Register Delay<span class="_ _0"></span>-</span></div><div class="c x36 y94 w6 h16"><div class="t m0 x37 h15 y95 ff2 fsf fc1 sc0 ls68 ws0">tMRD</div></div><div class="t m0 x38 h15 y93 ff2 fsf fc1 sc0 ls1 ws0"> </div><div class="t m0 x24 h15 y96 ff2 fsf fc1 sc0 ls60 ws40"> <span class="_ _5"></span> <span class="_ _28"> </span> <span class="_ _5"></span>Initialization Done<span class="_ _10"> </span> </div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/bg4.jpg"><div class="t m0 x8 h2 y1 ff2 fs0 fc0 sc0 ls1 ws0">4</div><div class="t m0 x9 h8 y24 ff1 fs6 fc0 sc0 ls1f ws25">SDR SDRAM Controller </div><div class="t m0 x1 h2 y97 ff3 fs0 fc0 sc0 ls13 ws47">Figure 4. Command Generation FSM</div><div class="t m0 x1 h2 y98 ff2 fs0 fc0 sc0 ls4b ws48">Command Generation <span class="_ _4"></span>FSM will generate SDR SDRAM commands<span class="_ _4"></span>.</div><div class="t m0 x1 h2 y99 ff2 fs0 fc0 sc0 ls13 ws49">Read and Write access to the SDRAM are b<span class="_ _5"></span>urst or<span class="_ _0"></span>iented, accesses starts at a specified address and contin<span class="_ _4"></span>ue f<span class="_ _5"></span>or </div><div class="t m0 x1 h2 y9a ff2 fs0 fc0 sc0 ls12 ws4a">a progr<span class="_ _4"></span>ammed numb<span class="_ _4"></span>er of locations in a pro<span class="_ _4"></span>grammed<span class="_ _4"></span> sequence.<span class="_ _4"></span> Accesses begin with the registr<span class="_ _5"></span>a<span class="_ _0"></span>tion of an A<span class="_ _5"></span>CTIVE </div><div class="t m0 x1 h2 y9b ff2 fs0 fc0 sc0 lse ws4b">command, which is then f<span class="_ _4"></span>ollow<span class="_ _4"></span>ed by a READ or WRITE <span class="_ _4"></span><span class="ls9 ws4c">command. The add<span class="_ _4"></span>ress bits coinciden<span class="_ _4"></span>t with the A<span class="_ _5"></span>CTIVE </span></div><div class="t m0 x1 h2 y9c ff2 fs0 fc0 sc0 lsd ws4d">command are used to select<span class="_ _4"></span> the bank and ro<span class="_ _4"></span>w to be ac<span class="ls9 ws4e">cesse<span class="_ _4"></span>d. The address bits<span class="_ _4"></span> coincident with the READ or<span class="_ _4"></span> </span></div><div class="t m0 x1 h2 y9d ff2 fs0 fc0 sc0 lsa ws19">WRITE command are used to select<span class="_ _4"></span> the star<span class="_ _0"></span>ting column location f<span class="_ _5"></span>or the burs<span class="_ _4"></span>t access.</div><div class="t m0 x1 h2 y9e ff2 fs0 fc0 sc0 ls69 ws4f">The controller pr<span class="_ _4"></span>ovides prog<span class="_ _4"></span>rammab<span class="_ _5"></span>le READ or WRITE burs<span class="_ _4"></span>t lengths 1, 2, 4 o<span class="_ _4"></span>r 8 locations<span class="_ _4"></span>, or the full page<span class="_ _4"></span>, with a </div><div class="t m0 x1 h2 y9f ff2 fs0 fc0 sc0 ls6a ws50">bur<span class="_ _4"></span>st terminate option. An auto <span class="_ _4"></span>precharge funct<span class="_ _4"></span>ion ma<span class="_ _5"></span>y be enabled to pr<span class="_ _4"></span>ovide a r<span class="_ _4"></span>ow prechar<span class="_ _4"></span>ge that is initiated<span class="_ _4"></span> at </div><div class="t m0 x1 h2 ya0 ff2 fs0 fc0 sc0 ls6a ws21">the end of the b<span class="_ _5"></span>urst sequence.</div><div class="t m2 x39 h17 ya1 ff2 fs10 fc1 sc0 ls6b ws0">IDLE</div><div class="t m2 x37 h17 ya2 ff2 fs10 fc1 sc0 ls6c ws0">SELF </div><div class="t m2 x3a h17 ya3 ff2 fs10 fc1 sc0 ls6c ws0">REFR<span class="_ _0"></span>ESH</div><div class="t m2 x3b h17 ya4 ff2 fs10 fc1 sc0 ls6c ws0">AUTO </div><div class="t m2 x3c h17 ya5 ff2 fs10 fc1 sc0 ls6c ws0">REFR<span class="_ _0"></span>ESH</div><div class="t m2 x3d h17 ya6 ff2 fs10 fc1 sc0 ls6d ws0">LOAD MO<span class="_ _4"></span>DE</div><div class="t m2 x20 h17 ya7 ff2 fs10 fc1 sc0 ls6e ws0">REG</div><div class="t m2 x3e h17 ya8 ff2 fs10 fc1 sc0 ls6c ws0">PRECH<span class="_ _0"></span>ARGE</div><div class="t m3 x3f h18 ya9 ff2 fs11 fc1 sc0 ls6f ws0">i_selfrefres<span class="_ _4"></span>h_re<span class="ff4 ls1">q</span></div><div class="t m3 x40 h18 yaa ff2 fs11 fc1 sc0 ls70 ws0">i_refresh_<span class="_ _4"></span>re<span class="ff4 ls1">q</span></div><div class="t m3 x20 h18 yab ff2 fs11 fc1 sc0 ls71 ws0">i_loadmod_re<span class="ff4 ls1">q</span></div><div class="t m3 x41 h18 yac ff2 fs11 fc1 sc0 ls72 ws0">i_precharge_re<span class="ff4 ls1">q</span></div><div class="t m3 x42 h18 yad ff2 fs11 fc1 sc0 ls73 ws51">! (i_cp<span class="ff4 ls1 ws0">u<span class="ff2 ls74">_ad</span>v<span class="_ _4"></span><span class="ff2 ls75 ws52">n) &amp;&amp; </span></span></div><div class="t m3 x43 h18 yae ff2 fs11 fc1 sc0 ls76 ws0">o_init_done</div><div class="t m2 x39 h17 yaf ff2 fs10 fc1 sc0 ls6c ws0">ACTI<span class="_ _0"></span><span class="ff4 ls1">V<span class="ff2">E</span></span></div><div class="t m3 x30 h18 yb0 ff2 fs11 fc1 sc0 ls77 ws0">DONE_ACTI<span class="ff4 ls1">V</span><span class="ls74">E2R<span class="ff4 ls1">W</span><span class="ls78">_DE</span></span></div><div class="t m3 x44 h18 yb1 ff2 fs11 fc1 sc0 ls76 ws53">LA<span class="_ _4"></span>Y &amp;&amp; i_cp<span class="ff4 ls1 ws0">u<span class="ff2 ls79">_r</span>w</span><span class="ls79 ws54">n = 1 </span></div><div class="t m2 x45 h17 yb2 ff2 fs10 fc1 sc0 ls6c ws55">READ AU<span class="_ _0"></span>TO </div><div class="t m2 x46 h17 yb3 ff2 fs10 fc1 sc0 ls6e ws0">PRECHA<span class="_ _4"></span>RGE</div><div class="c x47 yb4 w7 h19"><div class="t m2 x48 h17 yb5 ff4 fs10 fc1 sc0 ls1 ws0">W<span class="ff2 ls7a ws56">RITE A<span class="_ _4"></span>UTO </span></div><div class="t m2 x48 h17 yb6 ff2 fs10 fc1 sc0 ls6c ws0">PRECH<span class="_ _0"></span>ARGE</div><div class="t m3 x49 h18 yb7 ff2 fs11 fc1 sc0 ls77 ws0">DONE_ACTI<span class="ff4 ls1">V</span><span class="ls74">E2R<span class="ff4 ls1">W</span><span class="ls79">_D</span></span></div><div class="t m3 x49 h18 yb8 ff2 fs11 fc1 sc0 ls76 ws57">ELA<span class="_ _4"></span>Y &amp;&amp; i_cp<span class="ff4 ls1 ws0">u<span class="ff2 ls7b">_r</span>w</span><span class="ws53">n = 0 </span></div><div class="t m2 x4a h17 yb9 ff2 fs10 fc1 sc0 ls6c ws58">CAS LA<span class="_ _4"></span>TENC<span class="_ _0"></span>Y</div><div class="t m2 x4a h17 yba ff2 fs10 fc1 sc0 ls7c ws59">READ DA<span class="_ _7"></span>T<span class="_ _5"></span>A</div><div class="t m3 x4b h18 ybb ff2 fs11 fc1 sc0 ls7d ws0">DONE_CAS_LA<span class="_ _4"></span>TENCY</div><div class="t m2 x4c h17 ybc ff2 fs10 fc1 sc0 ls6e ws5a">BURST<span class="_ _5"></span> STOP</div><div class="t m2 x4d h17 ybd ff2 fs10 fc1 sc0 ls6c ws0">READ</div><div class="t m2 x48 h17 ybe ff4 fs10 fc1 sc0 ls1 ws0">W<span class="ff2 ls7e ws5b">RITE DA<span class="_ _7"></span>T<span class="_ _5"></span>A</span></div><div class="t m3 x4e h18 ybf ff2 fs11 fc1 sc0 ls7f ws0">i_<span class="ff4 ls74">bu</span><span class="ls80">rststop_re<span class="ff4 ls1">q</span></span></div><div class="t m3 x4f h18 yc0 ff2 fs11 fc1 sc0 ls7f ws0">i_<span class="ff4 ls74">bu</span><span class="ls81">rststop_re<span class="_ _4"></span><span class="ff4 ls1">q</span></span></div><div class="t m2 x50 h17 yc1 ff2 fs10 fc1 sc0 ls82 ws5c">BURST STOP</div><div class="t m2 x51 h17 yc2 ff4 fs10 fc1 sc0 ls1 ws0">W<span class="ff2 ls7a">RITE</span></div><div class="t m3 x52 h18 yc3 ff2 fs11 fc1 sc0 ls77 ws0">DONE_READ_BURST</div><div class="t m2 x53 h17 yc4 ff2 fs10 fc1 sc0 ls83 ws0">DA<span class="_ _5"></span>T<span class="_ _5"></span>AIN2ACTI<span class="ff4 ls1">V<span class="_ _4"></span><span class="ff2">E</span></span></div><div class="t m3 x54 h18 yc5 ff2 fs11 fc1 sc0 ls84 ws0">DONE_<span class="ff4 ls1">W</span><span class="ls85">RITE_BURST</span></div><div class="t m3 x55 h18 yc6 ff2 fs11 fc1 sc0 ls85 ws0">DONE_DA<span class="_ _4"></span>T<span class="_ _4"></span>AIN2ACTI<span class="ff4 ls1">V<span class="ff2">E</span></span></div><div class="t m3 x56 h18 yc7 ff2 fs11 fc1 sc0 ls86 ws0">DONE_AUTOREFRESH_PERIOD</div><div class="t m3 x57 h18 yc8 ff2 fs11 fc1 sc0 ls87 ws0">DONE_SELFREFRESH</div><div class="t m3 x58 h18 yc9 ff2 fs11 fc1 sc0 ls88 ws0">2ACTI<span class="ff4 ls1">V</span>E_DELA<span class="_ _5"></span>Y</div><div class="t m3 x59 h18 yca ff2 fs11 fc1 sc0 ls89 ws0">DONE_LOAD_MO</div><div class="t m3 x5a h18 ycb ff2 fs11 fc1 sc0 ls87 ws0">DEREG_DELA<span class="_ _4"></span>Y</div><div class="t m3 x5b h18 ycc ff2 fs11 fc1 sc0 ls7d ws0">DONE_CAS_LA<span class="_ _4"></span>TENCY</div><div class="t m3 x5c h18 ycd ff2 fs11 fc1 sc0 ls84 ws0">DONE_<span class="ff4 ls1">W</span><span class="ls77">RITE_</span></div><div class="t m3 x5c h18 yce ff2 fs11 fc1 sc0 ls89 ws0">RECO<span class="ff4 ls1">V</span><span class="ls8a">ERY_DELA<span class="_ _5"></span>Y</span></div><div class="t m3 x2d h18 ycf ff2 fs11 fc1 sc0 ls8b ws0">DONE_PRECHARGE_PERIOD</div></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89959206/bg5.jpg"><div class="t m0 x8 h2 y1 ff2 fs0 fc0 sc0 ls1 ws0">5</div><div class="t m0 x9 h8 y24 ff1 fs6 fc0 sc0 ls1f ws25">SDR SDRAM Controller </div><div class="t m0 x1 h5 y25 ff1 fs3 fc0 sc0 ls8c ws5d">Signal Description</div><div class="t m0 x1 h2 y26 ff3 fs0 fc0 sc0 ls21 ws27">T<span class="_ _7"></span>able 2. Sign<span class="_ _4"></span>al Description</div><div class="t m0 x1 h5 yd0 ff1 fs3 fc0 sc0 ls8d ws5e">Initialization Conditions</div><div class="t m0 x1 h2 yd1 ff2 fs0 fc0 sc0 ls8e ws5f">An asynchro<span class="_ _0"></span>nous active low reset signal as<span class="_ _0"></span>ser<span class="_ _0"></span>tio<span class="_ _0"></span>n is ne<span class="ls8f ws60">cessar<span class="_ _9"></span>y to initialize the SDR <span class="_ _4"></span>SD<span class="_ _5"></span>AM Controller to proper </span></div><div class="t m0 x1 h2 yd2 ff2 fs0 fc0 sc0 ls9 ws21">operat<span class="_ _4"></span>ing state.</div><div class="t m0 x5d h3 yd3 ff1 fs1 fc0 sc0 ls90 ws0">Signal<span class="_ _29"> </span>Width<span class="_ _2a"> </span>T<span class="_ _5"></span>ype<span class="_ _2b"> </span>Description</div><div class="t m0 x5e h3 yd4 ff2 fs1 fc0 sc0 ls2 ws61">i_clk<span class="_ _2c"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>System Clock</div><div class="t m0 x5e h3 yd5 ff2 fs1 fc0 sc0 ls91 ws62">i_rst<span class="_ _2e"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Asynchronous Active lo<span class="_ _4"></span>w Reset</div><div class="t m0 x5e h3 yd6 ff2 fs1 fc0 sc0 ls4c ws63">i_advn<span class="_ _2f"> </span>1<span class="_ _1f"> </span>Input<span class="_ _2d"> </span>Active low Address enab<span class="_ _4"></span>le f<span class="_ _4"></span>or Activ<span class="_ _4"></span>e state</div><div class="t m0 x5e h3 yd7 ff2 fs1 fc0 sc0 ls92 ws64">i_rwn<span class="_ _30"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>R/W Enable: 1-Read,0-Write</div><div class="t m0 x5e h3 yd8 ff2 fs1 fc0 sc0 ls91 ws0">i_addr<span class="_ _31"> </span>[RO<span class="_ _5"></span>W<span class="_ _4"></span>ADDR_MSB:COLADDR_LS</div><div class="t m0 x49 h3 yd9 ff2 fs1 fc0 sc0 ls93 ws0">B]</div><div class="t m0 x5f h3 yda ff2 fs1 fc0 sc0 ls94 ws0">Input</div><div class="t m0 x60 h3 yd8 ff2 fs1 fc0 sc0 ls90 ws65">Input Address to SDRAM Controller</div><div class="t m0 x5e h3 ydb ff2 fs1 fc0 sc0 ls95 ws66">i_selfrefrresh_req<span class="_ _32"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Request for Self <span class="_ _4"></span>Refresh</div><div class="t m0 x5e h3 ydc ff2 fs1 fc0 sc0 ls96 ws67">i_loadmod_req<span class="_ _33"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Request for Loading Mode Register</div><div class="t m0 x5e h3 ydd ff2 fs1 fc0 sc0 ls97 ws68">i_burststop_req<span class="_ _34"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Request for Burst Stop</div><div class="t m0 x5e h3 yde ff2 fs1 fc0 sc0 ls98 ws69">i_disable_activ<span class="_ _4"></span>e<span class="_ _35"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Disables opening a row if already opened</div><div class="t m0 x5e h3 ydf ff2 fs1 fc0 sc0 ls97 ws68">i_disable_precharge<span class="_ _36"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Disables precharge, k<span class="_ _5"></span>eep op<span class="_ _0"></span>en for ne<span class="_ _5"></span>xt R/W</div><div class="t m0 x5e h3 ye0 ff2 fs1 fc0 sc0 ls97 ws68">i_precharge_req<span class="_ _37"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Request for precharge</div><div class="t m0 x5e h3 ye1 ff2 fs1 fc0 sc0 ls96 ws67">i_data<span class="_ _38"> </span>[CPU_D<span class="_ _4"></span>A<span class="_ _7"></span>T<span class="_ _6"></span>A_WIDTH-1<span class="_ _0"></span>:0]<span class="_ _1b"> </span>Input<span class="_ _2d"> </span>Input data to the SDRAM Controlle<span class="_ _0"></span>r</div><div class="t m0 x5e h3 ye2 ff2 fs1 fc0 sc0 ls96 ws6a">i_power_down<span class="_ _39"> </span>1<span class="_ _1f"> </span>In<span class="_ _0"></span>put<span class="_ _2d"> </span>Enables pow<span class="_ _4"></span>er down mode if high</div><div class="t m0 x5e h3 ye3 ff2 fs1 fc0 sc0 ls99 ws6b">i_disable_autorefresh<span class="_ _3a"> </span>1<span class="_ _3b"> </span>Input<span class="_ _2d"> </span>Disables auto refresh</div><div class="t m0 x5e h3 ye4 ff2 fs1 fc0 sc0 ls92 ws0">o_data<span class="_ _3c"> </span>[CPU_D<span class="_ _4"></span>A<span class="_ _7"></span>T<span class="_ _6"></span>A_WIDTH-1:0<span class="_ _0"></span>]<span class="_ _23"> </span>Output<span class="_ _3d"> </span>Out<span class="ls1e ws6c">put data from the SDRAM Controller</span></div><div class="t m0 x5e h3 ye5 ff2 fs1 fc0 sc0 ls98 ws0">o_write_do<span class="_ _0"></span>ne</div><div class="t m0 x61 h3 ye6 ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 ye5 ff2 fs1 fc0 sc0 ls97 ws6d">When High, indicates that wr<span class="_ _0"></span>ite to SDRAM <span class="_ _0"></span>is com-</div><div class="t m0 x60 h3 ye7 ff2 fs1 fc0 sc0 ls9a ws0">plete</div><div class="t m0 x5e h3 ye8 ff2 fs1 fc0 sc0 ls9b ws0">o_read_done</div><div class="t m0 x61 h3 ye9 ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 ye8 ff2 fs1 fc0 sc0 ls3 ws6e">When High, indi<span class="_ _0"></span>cates t<span class="ls4c ws63">hat read from SDRAM is </span></div><div class="t m0 x60 h3 yea ff2 fs1 fc0 sc0 ls9c ws0">complete</div><div class="t m0 x5e h3 yeb ff2 fs1 fc0 sc0 ls96 ws0">o_data_valid</div><div class="t m0 x61 h3 yec ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 yeb ff2 fs1 fc0 sc0 ls1e ws6c">Output data valid, <span class="_ _4"></span>can be used for FIFO Write </div><div class="t m0 x60 h3 yed ff2 fs1 fc0 sc0 ls9d ws0">Enable </div><div class="t m0 x5e h3 yee ff2 fs1 fc0 sc0 ls2 ws0">o_data_req</div><div class="t m0 x61 h3 yef ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 yee ff2 fs1 fc0 sc0 ls2 ws2">Input data request, can be used for FIFO read </div><div class="t m0 x60 h3 yf0 ff2 fs1 fc0 sc0 ls9e ws0">Enable</div><div class="t m0 x5e h3 yf1 ff2 fs1 fc0 sc0 ls98 ws0">o_busy</div><div class="t m0 x61 h3 yf2 ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 yf1 ff2 fs1 fc0 sc0 ls4f ws6f">Active<span class="_ _4"></span> low b<span class="_ _5"></span>u<span class="_ _0"></span>sy signal which indicates SDRAM </div><div class="t m0 x60 h3 yf3 ff2 fs1 fc0 sc0 ls95 ws70">Controller is busy</div><div class="t m0 x5e h3 yf4 ff2 fs1 fc0 sc0 ls95 ws71">o_init_done<span class="_ _22"> </span>1<span class="_ _38"> </span>Output<span class="_ _3f"> </span>Indicates Initialization of SDRAM is completed</div><div class="t m0 x5e h3 yf5 ff2 fs1 fc0 sc0 ls3 ws0">o_ack</div><div class="t m0 x61 h3 yf6 ff2 fs1 fc0 sc0 ls97 ws0">1<span class="_ _3e"> </span>Output</div><div class="t m0 x60 h3 yf5 ff2 fs1 fc0 sc0 ls97 ws62">Indicates controller is about to star<span class="_ _9"></span>t write, read, or </div><div class="t m0 x60 h3 yf7 ff2 fs1 fc0 sc0 ls9f ws72">load mode register o<span class="_ _0"></span>peration </div><div class="t m0 x5e h3 yf8 ff2 fs1 fc0 sc0 ls95 ws66">o_sdram_addr<span class="_ _40"> </span>[SDRAM_ADDR_WIDTH-1:0]<span class="_ _41"> </span>Output<span class="_ _3d"> </span>SDRAM address</div><div class="t m0 x5e h3 yf9 ff2 fs1 fc0 sc0 lsa0 ws0">o_sdram_blkaddr<span class="_ _42"> </span>[SDRAM_BLKADR_WIDTH-<span class="ls1e ws6c">1:0]<span class="_ _43"> </span>Output<span class="_ _3d"> </span>SDRAM Bank Address</span></div><div class="t m0 x5e h3 yfa ff2 fs1 fc0 sc0 ls95 ws66">o_sdram_casn<span class="_ _2b"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM column select</div><div class="t m0 x5e h3 yfb ff2 fs1 fc0 sc0 ls95 ws66">o_sdram_ck<span class="_ _5"></span>e<span class="_ _44"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM Clock Enable</div><div class="t m0 x5e h3 yfc ff2 fs1 fc0 sc0 ls54 ws38">o_sdram_csn<span class="_ _45"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM Chip Select</div><div class="t m0 x5e h3 yfd ff2 fs1 fc0 sc0 ls54 ws0">o_sdram_dqm<span class="_ _46"> </span>[SDRAM_DQM_WIDTH-<span class="lsa1 ws73">1:0]<span class="_ _47"> </span>Output<span class="_ _3d"> </span>SDRAM Data Mask</span></div><div class="t m0 x5e h3 yfe ff2 fs1 fc0 sc0 ls91 ws62">o_sdram_rasn<span class="_ _48"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM row address select</div><div class="t m0 x5e h3 yff ff2 fs1 fc0 sc0 ls91 ws68">o_sdram_wen<span class="_ _49"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM wr<span class="_ _0"></span>ite enable</div><div class="t m0 x5e h3 y100 ff2 fs1 fc0 sc0 ls92 ws71">o_sdram_clk<span class="_ _4a"> </span>1<span class="_ _3e"> </span>Output<span class="_ _3d"> </span>SDRAM clock</div><div class="t m0 x5e h3 y101 ff2 fs1 fc0 sc0 ls1e ws0">i_sdram_dq<span class="_ _4b"> </span>[SDRAM_D<span class="_ _5"></span>A<span class="_ _7"></span>T<span class="_ _7"></span>A_WIDTH<span class="lsa2 ws74">-1:0]<span class="_ _4c"> </span>Input<span class="_ _2d"> </span>SD<span class="_ _4"></span>RAM input da<span class="_ _4"></span>ta</span></div><div class="t m0 x5e h3 y102 ff2 fs1 fc0 sc0 ls91 ws62">o_sdram_dq<span class="_ _4d"> </span>[SDRAM_D<span class="_ _4"></span>A<span class="_ _7"></span>T<span class="_ _6"></span>A_WIDTH-1:0]<span class="_ _47"> </span>Output<span class="_ _3d"> </span>SDRAM output data</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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