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LibFT4222-v1.4.4.zip
大小:4.39MB
价格:36积分
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5.0
上传者:u013516203
更新日期:2025-09-22

LibFT4222-v1.4.4.zip

资源文件列表(大概)

文件名
大小
LibFT4222-v1.4.4/
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LibFT4222-v1.4.4/FT4222H_Lib_1.4.4_Release_info.rtf
119.92KB
LibFT4222-v1.4.4/imports/
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LibFT4222-v1.4.4/imports/ftd2xx/
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LibFT4222-v1.4.4/imports/ftd2xx/amd64/
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LibFT4222-v1.4.4/imports/ftd2xx/amd64/ftd2xx.lib
19.79KB
LibFT4222-v1.4.4/imports/ftd2xx/ftd2xx.h
40.01KB
LibFT4222-v1.4.4/imports/ftd2xx/i386/
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LibFT4222-v1.4.4/imports/ftd2xx/i386/ftd2xx.lib
21.67KB
LibFT4222-v1.4.4/imports/LibFT4222/
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LibFT4222-v1.4.4/imports/LibFT4222/dll/
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LibFT4222-v1.4.4/imports/LibFT4222/dll/amd64/
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LibFT4222-v1.4.4/imports/LibFT4222/dll/amd64/LibFT4222-64.dll
205.61KB
LibFT4222-v1.4.4/imports/LibFT4222/dll/amd64/LibFT4222-64.lib
13.66KB
LibFT4222-v1.4.4/imports/LibFT4222/dll/i386/
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LibFT4222-v1.4.4/imports/LibFT4222/dll/i386/LibFT4222.dll
158KB
LibFT4222-v1.4.4/imports/LibFT4222/dll/i386/LibFT4222.lib
13.64KB
LibFT4222-v1.4.4/imports/LibFT4222/dll/LibFT4222.dll
158KB
LibFT4222-v1.4.4/imports/LibFT4222/dll/LibFT4222.lib
13.64KB
LibFT4222-v1.4.4/imports/LibFT4222/inc/
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LibFT4222-v1.4.4/imports/LibFT4222/inc/LibFT4222.h
13.43KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/
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LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/
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LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_atomic-vc100-mt-1_54.lib
7.85KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_chrono-vc100-mt-1_54.lib
430.32KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_date_time-vc100-mt-1_54.lib
747.73KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_exception-vc100-mt-1_54.lib
5.3KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_system-vc100-mt-1_54.lib
100.88KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/libboost_thread-vc100-mt-1_54.lib
1.25MB
LibFT4222-v1.4.4/imports/LibFT4222/lib/amd64/LibFT4222-64.lib
3.05MB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/
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LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_atomic-vc100-mt-1_54.lib
7.79KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_chrono-vc100-mt-1_54.lib
347.65KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_date_time-vc100-mt-1_54.lib
612.2KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_exception-vc100-mt-1_54.lib
5.35KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_system-vc100-mt-1_54.lib
81.67KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/libboost_thread-vc100-mt-1_54.lib
991.14KB
LibFT4222-v1.4.4/imports/LibFT4222/lib/i386/LibFT4222.lib
2.77MB
LibFT4222-v1.4.4/samples/
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LibFT4222-v1.4.4/samples/csharp_spi_master/
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LibFT4222-v1.4.4/samples/csharp_spi_master/csharp_spi_master.csproj
2.5KB
LibFT4222-v1.4.4/samples/csharp_spi_master/csharp_spi_master.sln
875B
LibFT4222-v1.4.4/samples/csharp_spi_master/FTD2XX_NET.dll
59KB
LibFT4222-v1.4.4/samples/csharp_spi_master/FTD2XX_NET.XML
74.91KB
LibFT4222-v1.4.4/samples/csharp_spi_master/Program.cs
11.1KB
LibFT4222-v1.4.4/samples/csharp_spi_master/Properties/
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LibFT4222-v1.4.4/samples/csharp_spi_master/Properties/AssemblyInfo.cs
1.41KB
LibFT4222-v1.4.4/samples/flash_example/
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LibFT4222-v1.4.4/samples/flash_example/doc/
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LibFT4222-v1.4.4/samples/flash_example/doc/MX25L6435E, 3V, 64Mb, v1.2.pdf
1.4MB
LibFT4222-v1.4.4/samples/flash_example/doc/TC58CVG2S0HRAIG_REV1.00_E20160622C.PDF
976.22KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_mxic/
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LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_mxic/spi_flash_quad_test_mxic.cpp
10.48KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_mxic/spi_flash_quad_test_mxic.pro
616B
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_mxic/spi_flash_quad_test_mxic.vcxproj
9.02KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_mxic/spi_flash_quad_test_mxic_static.pro
648B
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_toshiba/
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LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_toshiba/spi_flash_quad_test_toshiba.cpp
19.22KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_toshiba/spi_flash_quad_test_toshiba.pro
622B
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_toshiba/spi_flash_quad_test_toshiba.vcxproj
9.04KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_quad_test_toshiba/spi_flash_quad_test_toshiba_static.pro
654B
LibFT4222-v1.4.4/samples/flash_example/spi_flash_single_test_mxic/
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LibFT4222-v1.4.4/samples/flash_example/spi_flash_single_test_mxic/spi_flash_single_test_mxic.cpp
9.9KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_single_test_mxic/spi_flash_single_test_mxic.pro
620B
LibFT4222-v1.4.4/samples/flash_example/spi_flash_single_test_mxic/spi_flash_single_test_mxic.vcxproj
9.03KB
LibFT4222-v1.4.4/samples/flash_example/spi_flash_single_test_mxic/spi_flash_single_test_mxic_static.pro
652B
LibFT4222-v1.4.4/samples/getting_started/
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LibFT4222-v1.4.4/samples/getting_started/getting_started.cpp
3.71KB
LibFT4222-v1.4.4/samples/getting_started/getting_started.pro
588B
LibFT4222-v1.4.4/samples/getting_started/getting_started.vcxproj
9.11KB
LibFT4222-v1.4.4/samples/getting_started/getting_started_static.pro
621B
LibFT4222-v1.4.4/samples/gpio_read/
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LibFT4222-v1.4.4/samples/gpio_read/gpio_read.cpp
6.35KB
LibFT4222-v1.4.4/samples/gpio_read/gpio_read.pro
576B
LibFT4222-v1.4.4/samples/gpio_read/gpio_read.vcxproj
8.87KB
LibFT4222-v1.4.4/samples/gpio_read/gpio_read_static.pro
611B
LibFT4222-v1.4.4/samples/gpio_write/
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LibFT4222-v1.4.4/samples/gpio_write/gpio_write.cpp
3.71KB
LibFT4222-v1.4.4/samples/gpio_write/gpio_write.pro
578B
LibFT4222-v1.4.4/samples/gpio_write/gpio_write.vcxproj
8.87KB
LibFT4222-v1.4.4/samples/gpio_write/gpio_write_static.pro
613B
LibFT4222-v1.4.4/samples/i2c_master/
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LibFT4222-v1.4.4/samples/i2c_master/i2c_master.cpp
4.37KB
LibFT4222-v1.4.4/samples/i2c_master/i2c_master.pro
578B
LibFT4222-v1.4.4/samples/i2c_master/i2c_master.vcxproj
8.87KB
LibFT4222-v1.4.4/samples/i2c_master/i2c_master_static.pro
613B
LibFT4222-v1.4.4/samples/i2c_slave/
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LibFT4222-v1.4.4/samples/i2c_slave/i2c_slave.cpp
4.84KB
LibFT4222-v1.4.4/samples/i2c_slave/i2c_slave.pro
576B
LibFT4222-v1.4.4/samples/i2c_slave/i2c_slave.vcxproj
8.58KB
LibFT4222-v1.4.4/samples/i2c_slave/i2c_slave_static.pro
611B
LibFT4222-v1.4.4/samples/interrupt/
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LibFT4222-v1.4.4/samples/interrupt/interrupt.cpp
6.19KB
LibFT4222-v1.4.4/samples/interrupt/interrupt.pro
576B
LibFT4222-v1.4.4/samples/interrupt/interrupt.vcxproj
8.57KB
LibFT4222-v1.4.4/samples/interrupt/interrupt_static.pro
611B
LibFT4222-v1.4.4/samples/LibFT4222_examples.sln
7.77KB
LibFT4222-v1.4.4/samples/spi_master/
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LibFT4222-v1.4.4/samples/spi_master/spi_master.cpp
3.41KB
LibFT4222-v1.4.4/samples/spi_master/spi_master.pro
578B
LibFT4222-v1.4.4/samples/spi_master/spi_master.vcxproj
15.85KB
LibFT4222-v1.4.4/samples/spi_master/spi_master_static.pro
613B
LibFT4222-v1.4.4/samples/spi_slave_test_master_side/
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LibFT4222-v1.4.4/samples/spi_slave_test_master_side/spi_slave_test_master_side.cpp
12.22KB
LibFT4222-v1.4.4/samples/spi_slave_test_master_side/spi_slave_test_master_side.pro
608B
LibFT4222-v1.4.4/samples/spi_slave_test_master_side/spi_slave_test_master_side.vcxproj
9KB
LibFT4222-v1.4.4/samples/spi_slave_test_master_side/spi_slave_test_master_side_static.pro
643B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol/
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LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol/spi_slave_test_no_protocol.cpp
5.03KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol/spi_slave_test_no_protocol.pro
610B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol/spi_slave_test_no_protocol.vcxproj
8.7KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol/spi_slave_test_no_protocol_static.pro
645B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_master_side/
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LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_master_side/spi_slave_test_no_protocol_master_side.cpp
8.29KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_master_side/spi_slave_test_no_protocol_master_side.pro
634B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_master_side/spi_slave_test_no_protocol_master_side.vcxproj
9.09KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_master_side/spi_slave_test_no_protocol_master_side_static.pro
669B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_slave_side/
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LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_slave_side/spi_slave_test_no_protocol_slave_side.cpp
8.85KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_slave_side/spi_slave_test_no_protocol_slave_side.pro
632B
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_slave_side/spi_slave_test_no_protocol_slave_side.vcxproj
9.08KB
LibFT4222-v1.4.4/samples/spi_slave_test_no_protocol_slave_side/spi_slave_test_no_protocol_slave_side_static.pro
669B
LibFT4222-v1.4.4/samples/spi_slave_test_slave_side/
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LibFT4222-v1.4.4/samples/spi_slave_test_slave_side/spi_slave_test_slave_side.cpp
7.01KB
LibFT4222-v1.4.4/samples/spi_slave_test_slave_side/spi_slave_test_slave_side.pro
608B
LibFT4222-v1.4.4/samples/spi_slave_test_slave_side/spi_slave_test_slave_side.vcxproj
8.99KB
LibFT4222-v1.4.4/samples/spi_slave_test_slave_side/spi_slave_test_slave_side_static.pro
643B

资源内容介绍

LibFT4222-v1.4.4.zip
<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">1</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">P/N: PM1784</div><div class="t m0 x4 h4 y4 ff3 fs2 fc0 sc0 ls0 ws0">REV<span class="_ _0"></span>. 1.2, <span class="_ _1"></span>APR. 25, 2013</div><div class="t m2 x5 h5 y5 ff4 fs3 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m2 x6 h6 y6 ff4 fs4 fc0 sc0 ls0 ws0">HIGH PERFORMANCE</div><div class="t m2 x7 h6 y7 ff4 fs4 fc0 sc0 ls0 ws0">SERIAL<span class="_ _1"></span> FLASH SPECIFICA<span class="_ _2"></span>TION</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/bg2.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">2</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">P/N: PM1784</div><div class="t m0 x4 h4 y4 ff3 fs2 fc0 sc0 ls0 ws0">REV<span class="_ _0"></span>. 1.2, <span class="_ _1"></span>APR. 25, 2013</div><div class="t m0 x8 h7 y8 ff4 fs5 fc0 sc0 ls0 ws0">Contents</div><div class="t m0 x9 h8 y9 ff4 fs6 fc0 sc0 ls0 ws0">1. FEA<span class="_ _2"></span>TURES<span class="ws1"> ........................................................................................................................................................<span class="_"> </span></span>4</div><div class="t m0 x9 h8 ya ff4 fs6 fc0 sc0 ls0 ws0">2. GENERAL DESCRIPTION<span class="ws1"> ...............................................................................................................................<span class="_ _3"> </span></span>6</div><div class="t m0 xa h9 yb ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 1. Read Performance<span class="ws2"> .......................<span class="_ _1"></span>............................................................................................<span class="_ _4"></span><span class="ws0">6</span></span></div><div class="t m0 x9 h8 yc ff4 fs6 fc0 sc0 ls0 ws0">3. PIN CONFIGURA<span class="_ _2"></span>TION<span class="ws3"> ......................................................................................................................................<span class="_"> </span></span>7</div><div class="t m0 x9 h8 yd ff4 fs6 fc0 sc0 ls0 ws0">4. PIN DESCRIPTION<span class="ws4"> ............................................................................................................................................<span class="_ _3"> </span></span>7</div><div class="t m0 x9 h8 ye ff4 fs6 fc0 sc0 ls0 ws0">5. BLOCK DIAGRAM<span class="ws5"> .............................................................................................................................................<span class="_ _3"> </span></span>8</div><div class="t m0 x9 h8 yf ff4 fs6 fc0 sc0 ls0 ws0">6. DA<span class="_ _2"></span>T<span class="_ _0"></span>A<span class="_ _1"></span> PROTECTION<span class="ws6"> ..........................................................................................................................................<span class="_ _3"> </span></span>9</div><div class="t m0 xa h9 y10 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 2. Protected <span class="_ _2"></span>Area Sizes<span class="ws7"> ..............................................................................................................<span class="_ _4"></span></span>10</div><div class="t m0 xa ha y11 ff5 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 3. 4K-bit Secured OTP<span class="_ _1"></span> De&#59071;nition<span class="ff1 ws8"> ...............................................................................................<span class="_ _5"> </span><span class="ls1 ws9">11</span></span></div><div class="t m0 x9 h8 y12 ff4 fs6 fc0 sc0 ls0 ws0">7. MEMOR<span class="_ _1"></span>Y ORGANIZA<span class="_ _2"></span>TION<span class="wsa"> .............................................................................................................................<span class="_ _3"> </span></span>12</div><div class="t m0 xa h9 y13 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 4. Memory Organization<span class="wsb"> ............................................................................................<span class="_ _1"></span>.................<span class="_ _4"></span><span class="ws0">12</span></span></div><div class="t m0 x9 h8 y14 ff4 fs6 fc0 sc0 ls0 ws0">8. DEVICE OPERA<span class="_ _2"></span>TION<span class="wsc"> ......................................................................................................................................<span class="_ _6"> </span></span>13</div><div class="t m0 x9 h8 y15 ff4 fs6 fc0 sc0 ls0 ws0">9. HOLD FEA<span class="_ _2"></span>TURE<span class="wsd"> ..............................................................................................................................................<span class="_ _6"> </span></span>14</div><div class="t m0 x9 h8 y16 ff4 fs6 fc0 sc0 ls0 ws0">10. COMMAND DESCRIPTION<span class="wse"> ...........................................................................................................................<span class="_ _3"> </span></span>15</div><div class="t m0 xa h9 y17 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 5. Command Sets<span class="wsf"> ............................................................................................<span class="_ _1"></span>...........................<span class="_"> </span><span class="ws0">15</span></span></div><div class="t m0 xb h9 y18 ff1 fs6 fc0 sc0 ls0 ws0">10-1. <span class="_ _7"> </span>Write Enable (WREN)<span class="ws10"> ..........................................................................................................................<span class="_ _8"></span></span>18</div><div class="t m0 xb h9 y19 ff1 fs6 fc0 sc0 ls0 ws0">10-2. <span class="_ _7"> </span>Write Disable (WRDI)<span class="ws11"> ...........................................................................................................................<span class="_"> </span></span>19</div><div class="t m0 xb ha y1a ff5 fs6 fc0 sc0 ls0 ws0">10-3. <span class="_ _7"> </span>Read Identi&#59071;cation (RDID)<span class="ff1 ws12"> ...................................................................................................................<span class="_ _8"></span><span class="ws0">20</span></span></div><div class="t m0 xb h9 y1b ff1 fs6 fc0 sc0 ls0 ws0">10-4. <span class="_ _7"> </span>Read Status Register (RDSR)<span class="ws13"> .............................................................................................................<span class="_ _8"></span></span>21</div><div class="t m0 xb h9 y1c ff1 fs6 fc0 sc0 ls0 ws0">10-5. <span class="_ _7"> </span>Write Status Register (WRSR)<span class="ws14"> .............................................................................................................<span class="_"> </span></span>24</div><div class="t m0 xa h9 y1d ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 6. Protection Modes<span class="ws15"> .............................................................................................<span class="_ _1"></span>.......................<span class="_ _4"></span><span class="ws0">25</span></span></div><div class="t m0 xb h9 y1e ff1 fs6 fc0 sc0 ls0 ws0">10-6. <span class="_ _7"> </span>Read Data Bytes (READ)<span class="ws16"> ....................................................................................................................<span class="_ _8"></span></span>27</div><div class="t m0 xb h9 y1f ff1 fs6 fc0 sc0 ls0 ws0">10-7. <span class="_ _7"> </span>Read Data Bytes at Higher Speed (F<span class="_ _0"></span>AST_READ)<span class="ws17"> ..............................................................................<span class="_ _4"></span></span>28</div><div class="t m0 xb h9 y20 ff1 fs6 fc0 sc0 ls0 ws0">10-8. <span class="_ _7"> </span>Dual Read Mode (DREAD)<span class="ws12"> ..................................................................................................................<span class="_ _8"></span></span>29</div><div class="t m0 xb h9 y21 ff1 fs6 fc0 sc0 ls0 ws0">10-9. <span class="_ _7"> </span>2 x I/O Read Mode (2READ)<span class="ws18"> ...............................................................................................................<span class="_ _8"></span></span>30</div><div class="t m0 xb h9 y22 ff1 fs6 fc0 sc0 ls0 ws0">10-10. <span class="_ _4"></span>Quad Read Mode (QREAD)<span class="ws18"> ................................................................................................................<span class="_ _4"></span></span>31</div><div class="t m0 xb h9 y23 ff1 fs6 fc0 sc0 ls0 ws0">10-1<span class="_ _2"></span>1. <span class="_ _9"> </span>4 x I/O Read Mode (4READ)<span class="ws18"> ...............................................................................................................<span class="_ _8"></span></span>32</div><div class="t m0 xb h9 y24 ff1 fs6 fc0 sc0 ls0 ws0">10-12. <span class="_ _4"></span>Performance Enhance Mode<span class="ws19"> ...............................................................................................................<span class="_ _4"></span></span>33</div><div class="t m0 xb h9 y25 ff1 fs6 fc0 sc0 ls0 ws0">10-13. <span class="_ _4"></span>Performance Enhance Mode Reset (FFh)<span class="ws1a"> ...........................................................................................<span class="_"> </span></span>33</div><div class="t m0 xb h9 y26 ff1 fs6 fc0 sc0 ls0 ws0">10-14. <span class="_ _4"></span>Sector Erase (SE)<span class="ws1b"> ................................................................................................................................<span class="_ _4"></span></span>36</div><div class="t m0 xb h9 y27 ff1 fs6 fc0 sc0 ls0 ws0">10-15. <span class="_ _4"></span>Block Erase (BE)<span class="ws1c"> .................................................................................................................................<span class="_ _4"></span></span>37</div><div class="t m0 xb h9 y28 ff1 fs6 fc0 sc0 ls0 ws0">10-16. <span class="_ _4"></span>Block Erase (BE32K)<span class="ws13"> ...........................................................................................................................<span class="_ _4"></span></span>38</div><div class="t m0 xb h9 y29 ff1 fs6 fc0 sc0 ls0 ws0">10-17. <span class="_ _4"></span>Chip Erase (CE)<span class="ws1d"> ...................................................................................................................................<span class="_"> </span></span>39</div><div class="t m0 xb h9 y2a ff1 fs6 fc0 sc0 ls0 ws0">10-18. <span class="_ _4"></span>Page Program (PP)<span class="ws1e"> .............................................................................................................................<span class="_ _4"></span></span>40</div><div class="t m0 xb h9 y2b ff1 fs6 fc0 sc0 ls0 ws0">10-19. <span class="_ _4"></span>4 x I/O Page Program (4PP)<span class="ws12"> ................................................................................................................<span class="_ _4"></span></span>41</div><div class="t m0 xb h9 y2c ff1 fs6 fc0 sc0 ls0 ws0">10-20. <span class="_ _4"></span>Continuous Program mode (CP mode)<span class="ws1f"> ................................................................................................<span class="_ _4"></span></span>44</div><div class="t m0 xb h9 y2d ff1 fs6 fc0 sc0 ls0 ws0">10-21. <span class="_ _4"></span>Deep Power-down (DP)<span class="ws12"> .......................................................................................................................<span class="_ _4"></span></span>46</div><div class="t m0 xb h9 y2e ff1 fs6 fc0 sc0 ls0 ws0">10-22. <span class="_ _4"></span>Release from Deep Power-down (RDP), Read Electronic Signature (RES)<span class="ws20"> .......................................<span class="_ _4"></span></span>47</div><div class="t m0 xb h9 y2f ff1 fs6 fc0 sc0 ls0 ws0">10-23. <span class="_ _4"></span>Read Electronic Manufacturer ID &amp; Device ID (REMS), (REMS2), (REMS4)<span class="ws16"> .....................................<span class="_ _4"></span></span>49</div><div class="t m0 xb h9 y30 ff1 fs6 fc0 sc0 ls0 ws0">10-24. <span class="_ _4"></span>ID Read<span class="ws1d"> ................................................................................................................................................<span class="_"> </span></span>50</div><div class="t m0 xa ha y31 ff5 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 7. ID De&#59071;nitions <span class="ff1 wsb"> ............................................................................................<span class="_ _1"></span>.............................<span class="_ _4"></span><span class="ws0">50</span></span></div><div class="t m0 xb h9 y32 ff1 fs6 fc0 sc0 ls0 ws0">10-25. <span class="_ _4"></span>Enter Secured OTP (ENSO)<span class="ws21"> ................................................................................................................<span class="_ _8"></span></span>50</div><div class="t m0 xb h9 y33 ff1 fs6 fc0 sc0 ls0 ws0">10-26. <span class="_ _4"></span>Exit Secured OTP (EXSO)<span class="ws22"> ...................................................................................................................<span class="_"> </span></span>50</div><div class="t m0 xb h9 y34 ff1 fs6 fc0 sc0 ls0 ws0">10-27. <span class="_ _4"></span>Read Security Register (RDSCUR)<span class="ws23"> .....................................................................................................<span class="_ _4"></span></span>51</div><div class="t m0 xa ha y35 ff5 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 8. Security Register De&#59071;nition<span class="ff1 ws24"> ............................................................................................<span class="_ _1"></span>........<span class="_ _4"></span><span class="ws0">52</span></span></div><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/bg3.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">3</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">P/N: PM1784</div><div class="t m0 x4 h4 y4 ff3 fs2 fc0 sc0 ls0 ws0">REV<span class="_ _0"></span>. 1.2, <span class="_ _1"></span>APR. 25, 2013</div><div class="t m0 xc h9 y36 ff1 fs6 fc0 sc0 ls0 ws0">10-28. <span class="_ _4"></span>Write Security Register (WRSCUR)<span class="ws11"> .....................................................................................................<span class="_ _8"></span></span>53</div><div class="t m0 xc h9 y37 ff1 fs6 fc0 sc0 ls0 ws0">10-29. <span class="_ _4"></span>Write Protection Selection (WPSEL)<span class="ws25"> ....................................................................................................<span class="_ _8"></span></span>53</div><div class="t m0 xc h9 y38 ff1 fs6 fc0 sc0 ls0 ws0">10-30. <span class="_ _4"></span>Single Block Lock/Unlock Protection (SBLK/SBULK)<span class="ws26"> ..........................................................................<span class="_"> </span></span>57</div><div class="t m0 xc h9 y39 ff1 fs6 fc0 sc0 ls0 ws0">10-31. <span class="_ _4"></span>Read Block Lock Status (RDBLOCK)<span class="ws27"> ..................................................................................................<span class="_ _4"></span></span>60</div><div class="t m0 xc h9 y3a ff1 fs6 fc0 sc0 ls0 ws0">10-32. <span class="_ _4"></span>Gang Block Lock/Unlock (GBLK/GBULK)<span class="ws28"> ...........................................................................................<span class="_ _4"></span></span>61</div><div class="t m0 xc h9 y3b ff1 fs6 fc0 sc0 ls0 ws0">10-33. <span class="_ _4"></span>Enable SO to Output RY/BY# (ESRY)<span class="ws29"> .................................................................................................<span class="_ _8"></span></span>62</div><div class="t m0 xc h9 y3c ff1 fs6 fc0 sc0 ls0 ws0">10-34. <span class="_ _4"></span>Disable SO to Output RY/BY# (DSRY)<span class="ws2a"> ................................................................................................<span class="_ _8"></span></span>62</div><div class="t m0 xc h9 y3d ff1 fs6 fc0 sc0 ls0 ws0">10-35. <span class="_ _4"></span>No Operation (NOP)<span class="ws16"> ............................................................................................................................<span class="_ _4"></span></span>62</div><div class="t m0 xc h9 y3e ff1 fs6 fc0 sc0 ls0 ws0">10-36. <span class="_ _4"></span>Software Reset (Reset-Enable (RSTEN) and Reset (RST))<span class="ws2b"> ...............................................................<span class="_ _4"></span></span>62</div><div class="t m0 xc h9 y3f ff1 fs6 fc0 sc0 ls0 ws0">10-37. <span class="_ _4"></span>Read SFDP Mode (RDSFDP)<span class="ws2c"> ..............................................................................................................<span class="_ _8"></span></span>63</div><div class="t m0 xd ha y40 ff5 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 9. Signature and Parameter Identi&#59071;cation Data V<span class="_ _2"></span>alues <span class="ff1 ws2a"> .............................................................<span class="_ _8"></span><span class="ws0">64</span></span></div><div class="t m0 xd h9 y41 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 10. Parameter <span class="_ _1"></span>T<span class="_ _2"></span>able (0): JEDEC Flash Parameter <span class="_ _1"></span>T<span class="_ _2"></span>ables<span class="ws23"> .........................................................<span class="_ _8"></span></span>65</div><div class="t m0 xd h9 y42 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _2"></span>able 1<span class="_ _2"></span>1. Parameter T<span class="_ _a"></span>able (1): Macronix Flash Parameter T<span class="_ _a"></span>ables<span class="ws2d"> .......................................................<span class="_ _4"></span></span>67</div><div class="t m0 xe h8 y43 ff4 fs6 fc0 sc0 ls0 ws0">1<span class="_ _0"></span>1. POWER-ON ST<span class="_ _2"></span>A<span class="_ _0"></span>TE<span class="ws2e"> .......................................................................................................................................<span class="_ _6"> </span></span>69</div><div class="t m0 xe h8 y44 ff4 fs6 fc0 sc0 ls0 ws0">12. ELECTRICAL SPECIFICA<span class="_ _2"></span>TIONS</div><div class="t m0 xf h8 y45 ff4 fs6 fc0 sc0 ls0 ws2f"> ..................................................................................................................<span class="_ _3"> </span><span class="ws0">70</span></div><div class="t m0 xc h9 y46 ff1 fs6 fc0 sc0 ls0 ws0">12-1. <span class="_ _7"> </span>Absolute Maximum Ratings<span class="ws30"> .................................................................................................................<span class="_ _8"></span></span>70</div><div class="t m0 xc h9 y47 ff1 fs6 fc0 sc0 ls0 ws31">12-2. Capacitance<span class="ws12"> .........................................................................................................................................<span class="_ _8"></span><span class="ws0">70</span></span></div><div class="t m0 xd h9 y48 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _a"></span>able 12. DC Characteristics<span class="_ _8"></span><span class="ws32"> ................................................................................................................<span class="_ _8"></span></span>72</div><div class="t m0 xd h9 y49 ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _a"></span>able 13. <span class="_ _1"></span>AC Characteristics<span class="ws33"> ................................................................................................................<span class="_ _4"></span></span>73</div><div class="t m0 xe h8 y4a ff4 fs6 fc0 sc0 ls0 ws1">13. <span class="_ _8"></span>TIMING ANAL<span class="_ _2"></span>YSIS<span class="ws34"> ........................................................................................................................................<span class="_ _3"> </span><span class="ws0">75</span></span></div><div class="t m0 xd h9 y4b ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _a"></span>able 14. Power-Up T<span class="_ _1"></span>iming <span class="ws33"> .................................................................................................................<span class="_ _4"></span></span>77</div><div class="t m0 xc h9 y4c ff1 fs6 fc0 sc0 ls0 ws0">13-1. <span class="_ _7"> </span>Initial Delivery State<span class="ws13"> .............................................................................................................................<span class="_ _8"></span></span>77</div><div class="t m0 xe h8 y4d ff4 fs6 fc0 sc0 ls0 ws0">14. OPERA<span class="_ _2"></span>TING CONDITIONS<span class="ws35"> ...........................................................................................................................<span class="_ _6"> </span></span>78</div><div class="t m0 xe h8 y4e ff4 fs6 fc0 sc0 ls0 ws0">15. ERASE <span class="_ _1"></span>AND PROGRAMMING PERFORMANCE<span class="ws36"> ........................................................................................<span class="_ _6"> </span></span>80</div><div class="t m0 xe h8 y4f ff4 fs6 fc0 sc0 ls0 ws0">16. DA<span class="_ _2"></span>T<span class="_ _0"></span>A<span class="_ _1"></span> RETENTION<span class="ws37"> ........................................................................................................................................<span class="_"> </span></span>80</div><div class="t m0 xe h8 y50 ff4 fs6 fc0 sc0 ls0 ws0">17. LA<span class="_ _2"></span>TCH-UP CHARACTERISTICS<span class="ws36"> ..................................................................................................................<span class="_ _3"> </span></span>80</div><div class="t m0 xe h8 y51 ff4 fs6 fc0 sc0 ls0 ws0">18. ORDERING INFORMA<span class="_ _2"></span>TION<span class="wsa"> ..........................................................................................................................<span class="_ _6"> </span></span>81</div><div class="t m0 xe h8 y52 ff4 fs6 fc0 sc0 ls0 ws0">19. P<span class="_ _2"></span>ART NAME DESCRIPTION<span class="ws35"> .........................................................................................................................<span class="_ _6"> </span></span>82</div><div class="t m0 xe h8 y53 ff4 fs6 fc0 sc0 ls0 ws0">20. P<span class="_ _2"></span>ACKAGE INFORMA<span class="_ _0"></span>TION<span class="ws38"> ............................................................................................................................<span class="_ _3"> </span></span>83</div><div class="t m0 xe h8 y54 ff4 fs6 fc0 sc0 ls0 ws0">21. REVISION HISTOR<span class="_ _0"></span>Y <span class="ws39"> .....................................................................................................................................<span class="_ _3"> </span></span>88</div><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a><a class="l"><div class="d m3"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/bg4.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">4</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">P/N: PM1784</div><div class="t m0 x4 h4 y4 ff3 fs2 fc0 sc0 ls0 ws0">REV<span class="_ _0"></span>. 1.2, <span class="_ _1"></span>APR. 25, 2013</div><div class="t m4 x10 hb y55 ff4 fs7 fc0 sc0 ls0 ws0">64M-BIT [x 1/x 2/x 4] CMOS MXSMIO</div><div class="t m4 x11 hc y56 ff4 fs8 fc0 sc0 ls0 ws0">&#174;</div><div class="t m4 x12 hb y55 ff4 fs7 fc0 sc0 ls0 ws0"> (SERIAL MUL<span class="_ _2"></span>TI I/O) FLASH MEMOR<span class="_ _0"></span>Y</div><div class="t m0 x13 hb y57 ff4 fs7 fc0 sc0 ls0 ws0">1. FEA<span class="_ _2"></span>TURES</div><div class="t m0 x14 h8 y58 ff4 fs6 fc0 sc0 ls0 ws0">GENERAL</div><div class="t m0 x14 ha y59 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _9"> </span>Serial Peripheral Interface compatible -- Mode 0 and Mode 3</div><div class="t m0 x14 h8 y5a ff6 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _9"> </span><span class="ff1 ws3a">67,108,864 x 1 bit structure</span><span class="ff4"> <span class="_ _4"></span><span class="ff1 ws3a">or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O </span></span></div><div class="t m0 x15 h9 y5b ff1 fs6 fc0 sc0 ls0 ws0">mode) structure</div><div class="t m0 x14 ha y5c ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _9"> </span>2048 Equal Sectors with 4K bytes each </div><div class="t m0 x14 h9 y5d ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- <span class="_ _0"></span>Any Sector can be erased individually</div><div class="t m0 x14 ha y5e ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _c"> </span>256 Equal Blocks with 32K bytes each </div><div class="t m0 x14 h9 y5f ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- <span class="_ _0"></span>Any Block can be erased individually</div><div class="t m0 x14 ha y60 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _c"> </span>128 Equal Blocks with 64K bytes each </div><div class="t m0 x14 h9 y61 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- <span class="_ _0"></span>Any Block can be erased individually</div><div class="t m0 x14 ha y62 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _c"> </span>Power Supply Operation</div><div class="t m0 x14 h9 y63 ff1 fs6 fc0 sc0 ls0 ws0"> - 2.7 to 3.6 volt for read, erase, and program operations</div><div class="t m0 x14 ha y64 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; Latch-up protected to 100mA<span class="_ _0"></span> from -1V to Vcc +1V</div><div class="t m0 x14 h8 y65 ff4 fs6 fc0 sc0 ls0 ws0">PERFORMANCE</div><div class="t m0 x14 ha y66 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; High Performance</div><div class="t m0 x14 ha y67 ff5 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>VCC = 2.7~3.6V</div><div class="t m0 x14 h9 y68 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Normal read</div><div class="t m0 x14 h9 y69 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span> <span class="_ _d"> </span>- 50MHz</div><div class="t m0 x14 h9 y6a ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Fast read</div><div class="t m0 x14 h9 y6b ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span> <span class="_ _d"> </span>- 1 I/O: 104MHz with 8 dummy cycles </div><div class="t m0 xe h9 y6c ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span> <span class="_ _e"> </span>- 2 I/O: 86MHz with 4 dummy cycles for 2READ instruction</div><div class="t m0 x14 h9 y6d ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span> <span class="_ _d"> </span>- 4 I/O: Up to 104MHz</div><div class="t m0 x14 ha y6e ff5 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span> <span class="_ _d"> </span>- Con&#59071;gurable dummy cycle number for 4 I/O read operation</div><div class="t m0 xe h9 y6f ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Fast program time: 1.4ms(typ.) and 3ms(max.)/page (256-byte per page)</div><div class="t m0 x14 h9 y70 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Byte program time: 12us (typical)</div><div class="t m0 x14 h9 y71 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Continuous Program mode (automatically increase address under word program mode)</div><div class="t m0 x14 h9 y72 ff1 fs6 fc0 sc0 ls0 ws0"> - Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) / </div><div class="t m0 x15 h9 y73 ff1 fs6 fc0 sc0 ls0 ws0"> chip </div><div class="t m0 x14 ha y74 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; Low Power Consumption</div><div class="t m0 x14 h9 y75 ff1 fs6 fc0 sc0 ls0 ws0"> - Low active read current: 19mA(max.) at 104MHz, 10mA(max.) at 33MHz</div><div class="t m0 x14 h9 y76 ff1 fs6 fc0 sc0 ls0 ws0"> - Low active programming current: 25mA<span class="_ _0"></span> (max.)</div><div class="t m0 x14 h9 y77 ff1 fs6 fc0 sc0 ls0 ws0"> - Low active erase current: 25mA<span class="_ _0"></span> (max.)</div><div class="t m0 x14 h9 y78 ff1 fs6 fc0 sc0 ls0 ws0"> - Low standby current: 80uA<span class="_ _0"></span> (max.)</div><div class="t m0 x14 h9 y79 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Deep power down current: 40uA<span class="_ _0"></span> (max.) <span class="_ _f"> </span> <span class="_ _10"> </span> </div><div class="t m0 x14 ha y7a ff5 fs6 fc0 sc0 ls0 ws0">&#8226; T<span class="_ _2"></span>ypical 100,000 erase/program cycles</div><div class="t m0 x14 ha y7b ff5 fs6 fc0 sc0 ls0 ws0">&#8226; 20 years data retention<span class="ff4"> </span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89550280/bg5.jpg"><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">5</div><div class="t m1 x2 h3 y2 ff2 fs1 fc0 sc0 ls0 ws0">MX25L6435E</div><div class="t m0 x3 h4 y3 ff3 fs2 fc0 sc0 ls0 ws0">P/N: PM1784</div><div class="t m0 x4 h4 y4 ff3 fs2 fc0 sc0 ls0 ws0">REV<span class="_ _0"></span>. 1.2, <span class="_ _1"></span>APR. 25, 2013</div><div class="t m0 x14 h8 y7c ff4 fs6 fc0 sc0 ls0 ws0">SOFTW<span class="_ _0"></span>ARE FEA<span class="_ _2"></span>TURES</div><div class="t m0 x14 ha y7d ff5 fs6 fc0 sc0 ls0 ws0">&#8226; Input Data Format</div><div class="t m0 x14 h9 y7e ff1 fs6 fc0 sc0 ls0 ws0"> - 1-byte Command code</div><div class="t m0 x14 ha y7f ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _2"></span>Advanced Security Features</div><div class="t m0 x14 h9 y80 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- BP0-BP3 block group protect</div><div class="t m0 x14 ha y81 ff5 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- Flexible individual block protect when OTP WPSEL=1</div><div class="t m0 x14 ha y82 ff5 fs6 fc0 sc0 ls0 ws0"> <span class="_ _b"> </span>- <span class="_ _0"></span>Additional 4K bits secured OTP for unique identi&#59071;er</div><div class="t m0 x14 ha y83 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _2"></span>Auto Erase and <span class="_ _0"></span>Auto Program <span class="_ _0"></span>Algorithms</div><div class="t m0 x14 hd y84 ff1 fs9 fc0 sc0 ls0 ws0"> <span class="_ _a"></span>- </div><div class="t m0 xb ha y85 ff5 fs6 fc0 sc0 ls0 ws0">Automatically erases and veri&#59071;es data at selected sector</div><div class="t m0 x14 h9 y86 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x16 hd y87 ff1 fs9 fc0 sc0 ls0 ws0">- </div><div class="t m0 x17 ha y86 ff5 fs6 fc0 sc0 ls0 ws0">Automatically <span class="_ _4"></span>programs <span class="_ _4"></span>and <span class="_ _4"></span>veri&#59071;es <span class="_ _11"></span>data <span class="_ _4"></span>at <span class="_ _4"></span>selected <span class="_ _4"></span>page <span class="_ _11"></span>by <span class="_ _4"></span>an <span class="_ _4"></span>internal <span class="_ _4"></span>algorithm <span class="_ _11"></span>that <span class="_ _4"></span>automatically <span class="_ _4"></span>times </div><div class="t m0 x16 ha y88 ff5 fs6 fc0 sc0 ls0 ws0">the program pulse width (Any page to be programmed should have page in the erased state &#59071;rst.)</div><div class="t m0 x14 h9 y89 ff6 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="ff1">Status Register Feature</span></div><div class="t m0 x14 ha y8a ff6 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="ff5">Electronic Identi&#59071;cation</span></div><div class="t m0 x14 hd y8b ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x18 h9 y8c ff1 fs6 fc0 sc0 ls0 ws0">JEDEC 1-byte Manufacturer ID and 2-byte Device ID</div><div class="t m0 x14 h9 y8d ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _12"> </span>- RES command for 1-byte Device ID</div><div class="t m0 x14 h9 y8e ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _12"> </span>- The REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID</div><div class="t m0 x14 h9 y8f ff6 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="_ _13"> </span><span class="ff1">Support Serial Flash Discoverable Parameters (SFDP) mode</span></div><div class="t m0 x14 h8 y90 ff4 fs6 fc0 sc0 ls0 ws0">HARDW<span class="_ _0"></span>ARE FEA<span class="_ _0"></span>TURES</div><div class="t m0 x14 h9 y91 ff6 fs6 fc0 sc0 ls0 ws0">&#8226; <span class="ff1"> SCLK Input</span></div><div class="t m0 x14 hd y92 ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x17 h9 y93 ff1 fs6 fc0 sc0 ls0 ws0">Serial clock input</div><div class="t m0 x14 ha y94 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; SI/SIO0</div><div class="t m0 x14 hd y95 ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x17 h9 y96 ff1 fs6 fc0 sc0 ls0 ws0">Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode</div><div class="t m0 x14 ha y97 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; SO/SIO1</div><div class="t m0 x14 hd y98 ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x17 h9 y99 ff1 fs6 fc0 sc0 ls0 ws0">Serial Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode </div><div class="t m0 x14 ha y9a ff5 fs6 fc0 sc0 ls0 ws0">&#8226; WP#/SIO2</div><div class="t m0 x14 hd y9b ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x17 h9 y9c ff1 fs6 fc0 sc0 ls0 ws0">Hardware write protection or serial data Input/Output for 4 x I/O mode</div><div class="t m0 x14 ha y9d ff5 fs6 fc0 sc0 ls0 ws0">&#8226; HOLD#/SIO3</div><div class="t m0 x14 hd y9e ff1 fs9 fc0 sc0 ls0 ws0"> - </div><div class="t m0 x17 h9 y9f ff1 fs6 fc0 sc0 ls0 ws0">T<span class="_ _a"></span>o pause the device without deselecting the device or serial data Input/Output for 4 x I/O mode</div><div class="t m0 x14 ha ya0 ff5 fs6 fc0 sc0 ls0 ws0">&#8226; P<span class="_ _2"></span>ACKAGE</div><div class="t m0 x14 h9 ya1 ff1 fs6 fc0 sc0 ls0 ws0"> - 16-pin SOP (300mil)</div><div class="t m0 x14 h9 ya2 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x16 hd ya3 ff1 fs9 fc0 sc0 ls0 ws0">-</div><div class="t m0 x19 h9 ya2 ff1 fs6 fc0 sc0 ls0 ws0"> 8-pin SOP (200mil)</div><div class="t m0 x14 h9 ya4 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x16 hd ya5 ff1 fs9 fc0 sc0 ls0 ws0">-</div><div class="t m0 x19 h9 ya4 ff1 fs6 fc0 sc0 ls0 ws0"> 8-WSON (6x5mm, 8x6mm) </div><div class="t m0 x14 h9 ya6 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="_ _12"> </span>- 24 ball TFBGA<span class="_ _2"></span> (6x8mm)</div><div class="t m0 x14 h9 ya7 ff1 fs6 fc0 sc0 ls0 ws0"> </div><div class="t m0 x16 hd ya8 ff1 fs9 fc0 sc0 ls0 ws0">-</div><div class="t m0 x19 h8 ya7 ff1 fs6 fc0 sc0 ls0 ws0"> <span class="ff4">All devices are RoHS Compliant</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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