串口（UART）的FPGA实现工程源码

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基于Intel（Altera）的Quartus II平台的串口（UART）的FPGA实现工程源码：1、包括接收部分 + 发送部分；2、包含详细的仿真TB文件；3、起始位1bit，数据位8bit，停止位1bit，无奇偶校验；4、详细的说明文件请参考本人博文《https://wuzhikai.blog.csdn.net/article/details/114596930》。

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Legal Partition Candidates ;+-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;+-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+; issp_uart_rx_inst ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; uart_rx_isnt ; 3 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;+-------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+