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资源文件列表(大概)

文件名
大小
new/
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new/AES-FPGA-master能用/
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new/AES-FPGA-master能用/.gitignore
602B
new/AES-FPGA-master能用/aes_core/
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new/AES-FPGA-master能用/aes_core/aes_cipher_top.v
9.99KB
new/AES-FPGA-master能用/aes_core/aes_inv_cipher_top.v
11.41KB
new/AES-FPGA-master能用/aes_core/aes_inv_sbox.v
8.06KB
new/AES-FPGA-master能用/aes_core/aes_key_expand_128.v
3.82KB
new/AES-FPGA-master能用/aes_core/aes_rcon.v
3.68KB
new/AES-FPGA-master能用/aes_core/aes_sbox.v
8.05KB
new/AES-FPGA-master能用/aes_core/timescale.v
22B
new/AES-FPGA-master能用/aes_fpga.xise
37.44KB
new/AES-FPGA-master能用/aes_inv_test.v
1.34KB
new/AES-FPGA-master能用/aes_test.v
1.21KB
new/AES-FPGA-master能用/fuse.xmsgs
360B
new/AES-FPGA-master能用/README.md
477B
new/aes-master-能用/
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new/aes-master-能用/.gitattributes
83B
new/aes-master-能用/.github/
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new/aes-master-能用/.github/workflows/
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new/aes-master-能用/.github/workflows/ci.yml
1.21KB
new/aes-master-能用/.gitignore
568B
new/aes-master-能用/aes.core
1.17KB
new/aes-master-能用/data/
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new/aes-master-能用/data/sky130.tcl
199B
new/aes-master-能用/LICENSE
1.27KB
new/aes-master-能用/README.md
5.9KB
new/aes-master-能用/src/
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new/aes-master-能用/src/model/
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new/aes-master-能用/src/model/python/
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new/aes-master-能用/src/model/python/aes.py
33.69KB
new/aes-master-能用/src/model/python/aes_key_gen.py
22.29KB
new/aes-master-能用/src/model/python/rcon.py
23.37KB
new/aes-master-能用/src/rtl/
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new/aes-master-能用/src/rtl/aes.v
8.3KB
new/aes-master-能用/src/rtl/aes_core.v
10.31KB
new/aes-master-能用/src/rtl/aes_decipher_block.v
15.28KB
new/aes-master-能用/src/rtl/aes_encipher_block.v
14.08KB
new/aes-master-能用/src/rtl/aes_inv_sbox.v
11.2KB
new/aes-master-能用/src/rtl/aes_key_mem.v
12.47KB
new/aes-master-能用/src/rtl/aes_sbox.v
10.24KB
new/aes-master-能用/src/tb/
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new/aes-master-能用/src/tb/tb_aes.v
18.69KB
new/aes-master-能用/src/tb/tb_aes_core.v
17.13KB
new/aes-master-能用/src/tb/tb_aes_decipher_block.v
14.06KB
new/aes-master-能用/src/tb/tb_aes_encipher_block.v
18.2KB
new/aes-master-能用/src/tb/tb_aes_key_mem.v
24.6KB
new/aes-master-能用/toolruns/
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new/aes-master-能用/toolruns/Makefile
4KB
new/aes-verilog-master能用/
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new/aes-verilog-master能用/A0185646R_Pang Jia Jun Vernon.pdf
276.53KB
new/aes-verilog-master能用/part1-siso/
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new/aes-verilog-master能用/part1-siso/src/
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new/aes-verilog-master能用/part1-siso/src/AddRndKey_top.v
544B
new/aes-verilog-master能用/part1-siso/src/AEScntx.v
1.11KB
new/aes-verilog-master能用/part1-siso/src/AESCore.v
1.55KB
new/aes-verilog-master能用/part1-siso/src/aes_sbox.v
4.94KB
new/aes-verilog-master能用/part1-siso/src/AES_top.v
976B
new/aes-verilog-master能用/part1-siso/src/KeySchedule_top.v
1.41KB
new/aes-verilog-master能用/part1-siso/src/matrix_mult.v
642B
new/aes-verilog-master能用/part1-siso/src/MixCol_top.v
508B
new/aes-verilog-master能用/part1-siso/src/shiftRows_top.v
1.21KB
new/aes-verilog-master能用/part1-siso/src/subBytes_top.v
550B
new/aes-verilog-master能用/part1-siso/src/tb_aes.sv
4.24KB
new/aes-verilog-master能用/part1-siso/syn/
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new/aes-verilog-master能用/part1-siso/syn/.synopsys_dc.setup
436B
new/aes-verilog-master能用/part1-siso/syn/constraint.tcl
293B
new/aes-verilog-master能用/part1-siso/syn/synthesis.tcl
528B
new/aes-verilog-master能用/part1-siso/vcs/
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new/aes-verilog-master能用/part1-siso/vcs/makefile
395B
new/aes-verilog-master能用/part2-mimo/
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new/aes-verilog-master能用/part2-mimo/src/
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new/aes-verilog-master能用/part2-mimo/src/AddRndKey_top.v
544B
new/aes-verilog-master能用/part2-mimo/src/AEScntx.v
1.11KB
new/aes-verilog-master能用/part2-mimo/src/AESCore.v
1.55KB
new/aes-verilog-master能用/part2-mimo/src/aes_sbox.v
4.94KB
new/aes-verilog-master能用/part2-mimo/src/AES_top.v
1.24KB
new/aes-verilog-master能用/part2-mimo/src/KeySchedule_top.v
1.41KB
new/aes-verilog-master能用/part2-mimo/src/matrix_mult.v
642B
new/aes-verilog-master能用/part2-mimo/src/MixCol_top.v
508B
new/aes-verilog-master能用/part2-mimo/src/shiftRows_top.v
1.21KB
new/aes-verilog-master能用/part2-mimo/src/subBytes_top.v
550B
new/aes-verilog-master能用/part2-mimo/src/tb_aes.sv
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new/aes-verilog-master能用/part2-mimo/syn/
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new/aes-verilog-master能用/part2-mimo/syn/.synopsys_dc.setup
436B
new/aes-verilog-master能用/part2-mimo/syn/constraint.tcl
293B
new/aes-verilog-master能用/part2-mimo/syn/synthesis.tcl
528B
new/aes-verilog-master能用/part2-mimo/vcs/
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new/aes-verilog-master能用/part2-mimo/vcs/makefile
395B
new/aes-verilog-master能用/part3/
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new/aes-verilog-master能用/part3/src/
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new/aes-verilog-master能用/part3/src/AddRndKey_top.v
544B
new/aes-verilog-master能用/part3/src/AEScntx.v
1.5KB
new/aes-verilog-master能用/part3/src/AESCore.v
1.93KB
new/aes-verilog-master能用/part3/src/aes_sbox.v
4.94KB
new/aes-verilog-master能用/part3/src/AES_top.v
991B
new/aes-verilog-master能用/part3/src/KeySchedule_top.v
1.41KB
new/aes-verilog-master能用/part3/src/matrix_mult.v
642B
new/aes-verilog-master能用/part3/src/MixCol_top.v
508B
new/aes-verilog-master能用/part3/src/shiftRows_top.v
1.21KB
new/aes-verilog-master能用/part3/src/subBytes_top.v
550B
new/aes-verilog-master能用/part3/src/tb_aes.sv
4.08KB
new/aes-verilog-master能用/part3/syn/
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new/aes-verilog-master能用/part3/syn/.synopsys_dc.setup
436B
new/aes-verilog-master能用/part3/syn/constraint.tcl
297B
new/aes-verilog-master能用/part3/syn/synthesis.tcl
616B
new/aes-verilog-master能用/part3/vcs/
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new/aes-verilog-master能用/part3/vcs/makefile
395B
new/aes-verilog-master能用/README.md
244B
new/aes-verilog-master能用/ref/
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new/aes-verilog-master能用/ref/cipher_key.txt
322.46KB
new/aes-verilog-master能用/ref/cipher_text.txt
322.27KB
new/aes-verilog-master能用/ref/initial_round_data.txt
322.27KB
new/aes-verilog-master能用/ref/plain_text.txt
322.46KB
new/aes-verilog-master能用/ref/round1_data.txt
322.27KB
new/aes-verilog-master能用/ref/round2_data.txt
322.27KB
new/aes-verilog-master能用/ref/round3_data.txt
322.27KB
new/aes-verilog-master能用/ref/round4_data.txt
322.27KB
new/aes-verilog-master能用/ref/round5_data.txt
322.27KB
new/aes-verilog-master能用/ref/round6_data.txt
322.27KB
new/aes-verilog-master能用/ref/round7_data.txt
322.27KB
new/aes-verilog-master能用/ref/round8_data.txt
322.27KB
new/aes-verilog-master能用/ref/round9_data.txt
322.27KB
new/Hardware-Implementation-of-AES-main能用/
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new/Hardware-Implementation-of-AES-main能用/README.md
3.47KB
new/Hardware-Implementation-of-AES-main能用/src/
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new/Hardware-Implementation-of-AES-main能用/src/AddRoundKey.v
446B
new/Hardware-Implementation-of-AES-main能用/src/AES.v
2.57KB
new/Hardware-Implementation-of-AES-main能用/src/clock_gating.v
361B
new/Hardware-Implementation-of-AES-main能用/src/FSM_controller.v
4.58KB
new/Hardware-Implementation-of-AES-main能用/src/key_shedule.v
2.62KB
new/Hardware-Implementation-of-AES-main能用/src/MixColumns.v
1.24KB
new/Hardware-Implementation-of-AES-main能用/src/mux2_1.v
261B
new/Hardware-Implementation-of-AES-main能用/src/mux_4_1.v
370B
new/Hardware-Implementation-of-AES-main能用/src/RCON.v
378B
new/Hardware-Implementation-of-AES-main能用/src/README.md
3.24KB
new/Hardware-Implementation-of-AES-main能用/src/register.v
749B
new/Hardware-Implementation-of-AES-main能用/src/Shift_Rows.v
1.02KB
new/Hardware-Implementation-of-AES-main能用/src/SubByte.v
3.09KB
new/Hardware-Implementation-of-AES-main能用/src/S_BOX.v
5.11KB
new/Hardware-Implementation-of-AES-main能用/src/xor128.v
463B
new/Hardware-Implementation-of-AES-main能用/tb/
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new/Hardware-Implementation-of-AES-main能用/tb/AES_tb.v
843B

资源内容介绍

学习内容，之后学习使用
[![build-openlane-sky130](https://github.com/secworks/aes/actions/workflows/ci.yml/badge.svg?branch=master&event=push)](https://github.com/secworks/aes/actions/workflows/ci.yml)aes===Verilog implementation of the [symmetric block cipher AES (NIST FIPS 197)](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).## Status ##The core is completed, has been used in several FPGA and ASICdesigns. The core is well tested and mature.## Introduction ##This implementation supports 128 and 256 bit keys. Theimplementation is iterative and process one 128 block at a time. Blocksare processed on a word level with 4 S-boxes in the data path. TheS-boxes for encryption are shared with the key expansion and the corecan thus not do key update in parallel with block processing.The encipher and decipher block processing datapaths are separated andbasically self contained given access to a set of round keys and ablock. This makes it possible to hard wire the core to only encipher ordecipher operation. This allows the synthesis/build tools to optimizeaway the other functionality which will reduce the size to about50%. This has been tested to verify that decryption is removed and thecore still works.For cipher modes such as CTR, CCM, CMAC, GCM the decryptionfunctionality in the AES core will never be used and thus the decipherblock processing can be removed.This is a fairly compact implementation. Further reduction could beachived by just having a single S-box. Similarly the performane can beincreased by having 8 or even 16 S-boxes which would reduce the numberof cycles to two cycles for each round.## Branches ##There are several branches available that provides different versions ofthe core. The branches are not planned to be merged into master. Thebranches available that provides versions of the core are:### on-the-fly-keygen ###This version of AES implements the key expansion using an on-the-flymechanism. This allows the initial key expansion to be removed. Thissaves a number of cycles and also remove almost 1800 registers needed tostore the round keys. Note that this version of AES only supportsencryption. On-the-fly key generation does not work withdecryption. Decryption must be handled by the block cipher mode - forexample CTR.### dual-keys ###This version of AES supports two separate banks of expanded keys toallow fast key switching between two keys. This is useful for example inan AEAD mode with CBC + CMAC implemented using a single AES core.### cmt-sbox ###An experimental version of the core in which the S-box is implementedusing circuit minimized logic functions of a ROM table. The specifictable used is[the 113 gate circuit](http://cs-www.cs.yale.edu/homes/peralta/CircuitStuff/SLP_AES_113.txt) by the [CMT team at Yale](http://cs-www.cs.yale.edu/homes/peralta/CircuitStuff/CMT.html).Some area and performance results using the cmt_sbox compared tomaster.#### Altera- Tool: Quartus Prime 19.1.0- Device: Cyclone V (5CGXFC7C7F23C8)- master (S-box implemented with a table) - ALMs: 2599 - Regs: 3184 - Fmax: 93 MHz - aes_sbox: 160 ALUTs- cmt_sbox - ALMs: 2759 - Regs: 3147 - Fmax: 69 MHz - aes_sbox: 363 ALUTs#### Xilinx- Tool: Vivado 2019.2- Device: Kintex-7 (7k70tfbv676-1)- master: - LUTs: 3020 - FFs: 2992 - Fmax: 125 MHz- cmt_sbox: - LUTs: 2955 - FFs: 2992 - Fmax: 105 MHz## Core Usage### Usage sequence:1. Load the key to be used by writing to the key register words.2. Set the key length by writing to the config register.3. Initialize key expansion by writing a one to the init bit in the control register.4. Wait for the ready bit in the status register to be cleared and then to be set again. This means that the key expansion has been completed.5. Write the cleartext block to the block registers.6. Start block processing by writing a one to the next bit in the control register.7. Wait for the ready bit in the status register to be cleared and then to be set again. This means that the data block has been processed.8. Read out the ciphertext block from the result registers.## FuseSoCThis core is supported by the[FuseSoC](https://github.com/olofk/fusesoc) core package manager andbuild system. Some quick FuseSoC instructions:install FuseSoC~~~pip install fusesoc~~~Create and enter a new workspace~~~mkdir workspace && cd workspace~~~Register aes as a library in the workspace~~~fusesoc library add aes /path/to/aes~~~...if repo is available locally or......to get the upstream repo~~~fusesoc library add aes https://github.com/secworks/aes~~~To run lint~~~fusesoc run --target=lint secworks:crypto:aes~~~Run tb_aes testbench~~~fusesoc run --target=tb_aes secworks:crypto:aes~~~Run with modelsim instead of default tool (icarus)~~~fusesoc run --target=tb_aes --tool=modelsim secworks:crypto:aes~~~List all targets~~~fusesoc core show secworks:crypto:aes~~~## Implementation results - ASIC ##The core has been implemented in standard cell ASIC processes.### TSMC 180 nm ###Target frequency: 20 MHzComplete flow from RTL to placed gates. Automatic clock gating and scaninsertion.- 8 kCells- Aera: 520 x 520 um- Good timing margin with no big cells and buffers.## Implementation results - FPGA ##The core has been implemented in Altera and Xilinx FPGA devices.### Altera Cyclone V GX ###- 2624 ALMs- 3123 Regs- 96 MHz- 46 cycles/block### Altera Cyclone IV GX ###- 7426 LEs- 2994 Regs- 96 MHz fmax- 46 cycles/blockThis means that we can do more than 2 Mblocks/s or 256 Mbpsperformance.Removing the decipher module yields:- 5497 LEs- 2855 Regs- 106 MHz fmax- 46 cycles/block### Microchip IGLOO 2 ###- Tool: Libero v 12.4- Device: M2GL090TS-1FG484I- LUTs: 6335- SLEs: 1376- BRAMs: 8- Fmax: 98.5 MHz### Xilinx Spartan6LX-3 ###- 2576 slices- 3000 regs- 100 MHz- 46 cycles/block### Xilinx Artix 7 200T-3 ###- 2298 slices- 2989 regs- 97 MHz- 46 cycles/block

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