matlab技巧的全部合集
资源内容介绍
matlab技巧的全部合集 <link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/7/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">Intel</div><div class="t m0 x2 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">®</div><div class="t m0 x3 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0"> Agilex</div><div class="t m0 x4 h3 y2 ff1 fs1 fc0 sc0 ls0 ws0">™</div><div class="t m0 x5 h4 y1 ff2 fs0 fc0 sc1 ls0 ws0">时钟和<span class="_ _0"> </span><span class="ff1 sc0">PLL<span class="_ _0"> </span></span>用户指南</div><div class="t m0 x1 h5 y3 ff2 fs2 fc1 sc0 ls0 ws0">针对<span class="_ _1"> </span><span class="ff3">Intel</span></div><div class="t m0 x6 h6 y4 ff3 fs3 fc1 sc0 ls0 ws0">®</div><div class="t m0 x7 h7 y3 ff3 fs2 fc1 sc0 ls0 ws0"> Quartus</div><div class="t m0 x8 h6 y4 ff3 fs3 fc1 sc0 ls0 ws0">®</div><div class="t m0 x9 h5 y3 ff3 fs2 fc1 sc0 ls0 ws0"> Prime<span class="_ _1"> </span><span class="ff2">设计套件的更新：<span class="ff1">20.3</span></span></div><div class="t m0 x1 h5 y5 ff2 fs2 fc1 sc0 ls0 ws0">本翻译版本仅供参考，如果本翻译版本与其英文版本存在差异，则以英文版本为准。某些翻译版本尚未更新对应到最</div><div class="t m0 x1 h5 y6 ff2 fs2 fc1 sc0 ls0 ws0">新的英文版本，请参考</div><div class="t m0 xa h5 y7 ff2 fs2 fc0 sc1 ls0 ws0">英文版本<span class="fc1 sc0">以获取最新信息。</span></div><div class="t m0 xb h5 y8 ff2 fs2 fc0 sc1 ls0 ws0">在线版本</div><div class="t m0 xb h5 y9 ff2 fs2 fc0 sc1 ls0 ws0">发送反馈</div><div class="t m0 xc h7 ya ff1 fs2 fc0 sc0 ls0 ws0">UG-20216</div><div class="t m0 xd h7 yb ff3 fs2 fc1 sc0 ls0 ws0">ID: <span class="ff1 fc0">683761</span></div><div class="t m0 xe h5 yc ff2 fs2 fc1 sc0 ls0 ws0">版本<span class="ff3">: <span class="ff1 fc0">2021.12.13</span></span></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/bg2.jpg"><div class="t m0 xf h8 yd ff2 fs4 fc0 sc1 ls0 ws0">内容</div><div class="t m0 xf h7 ye ff1 fs2 fc1 sc0 ls0 ws0">1. Intel</div><div class="t m0 x10 h6 yf ff1 fs3 fc1 sc0 ls0 ws0">®</div><div class="t m0 x11 h7 ye ff1 fs2 fc1 sc0 ls0 ws0"> Agilex</div><div class="t m0 x12 h6 yf ff1 fs3 fc1 sc0 ls0 ws0">™</div><div class="t m0 x13 h5 ye ff1 fs2 fc1 sc0 ls0 ws0"> <span class="ff2 sc2">时钟和<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2 sc2">概述</span>..........................................................................................<span class="_ _2"> </span>4</div><div class="t m0 x14 h5 y10 ff3 fs2 fc1 sc0 ls0 ws0">1.1. <span class="ff2">时钟网络概述</span>..........................................................................................................<span class="_ _3"> </span>4</div><div class="t m0 x14 h5 y11 ff3 fs2 fc1 sc0 ls0 ws0">1.2. PLL<span class="_ _1"> </span><span class="ff2">概述</span>................................................................................................................<span class="_ _4"></span>4</div><div class="t m0 xf h5 y12 ff1 fs2 fc1 sc0 ls0 ws0">2. Intel Agilex <span class="ff2 sc2">时钟和<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2 sc2">架构和功能特性</span>................................................................................<span class="_"> </span>5</div><div class="t m0 x14 h5 y13 ff3 fs2 fc1 sc0 ls0 ws0">2.1. <span class="ff2">时钟网络架构和功能特性</span>............................................................................................<span class="_ _2"> </span>5</div><div class="t m0 x15 h5 y14 ff3 fs2 fc1 sc0 ls0 ws0">2.1.1. <span class="ff2">时钟网络架构</span>..............................................................................................<span class="_ _1"> </span>5</div><div class="t m0 x15 h5 y15 ff3 fs2 fc1 sc0 ls0 ws0">2.1.2. <span class="ff2">时钟资源</span>....................................................................................................<span class="_ _4"></span>7</div><div class="t m0 x15 h5 y16 ff3 fs2 fc1 sc0 ls0 ws0">2.1.3. <span class="ff2">时钟控制功能</span>..............................................................................................<span class="_ _1"> </span>8</div><div class="t m0 x14 h5 y17 ff3 fs2 fc1 sc0 ls0 ws0">2.2. PLL<span class="_ _1"> </span><span class="ff2">架构和功能特性</span>................................................................................................<span class="_ _1"> </span>10</div><div class="t m0 x15 h5 y18 ff3 fs2 fc1 sc0 ls0 ws0">2.2.1. PLL<span class="_ _1"> </span><span class="ff2">功能特性</span>.............................................................................................10</div><div class="t m0 x15 h5 y19 ff3 fs2 fc1 sc0 ls0 ws0">2.2.2. PLL<span class="_ _1"> </span><span class="ff2">使用</span>..................................................................................................<span class="_ _3"> </span>11</div><div class="t m0 x15 h5 y1a ff3 fs2 fc1 sc0 ls0 ws0">2.2.3. PLL<span class="_ _1"> </span><span class="ff2">位置</span>..................................................................................................<span class="_ _3"> </span>12</div><div class="t m0 x15 h5 y1b ff3 fs2 fc1 sc0 ls0 ws0">2.2.4. PLL<span class="_ _1"> </span><span class="ff2">架构</span>..................................................................................................<span class="_ _3"> </span>12</div><div class="t m0 x15 h5 y1c ff3 fs2 fc1 sc0 ls0 ws0">2.2.5. PLL<span class="_ _1"> </span><span class="ff2">控制信号</span>.............................................................................................13</div><div class="t m0 x15 h5 y1d ff3 fs2 fc1 sc0 ls0 ws0">2.2.6. PLL<span class="_ _1"> </span><span class="ff2">反馈模式</span>.............................................................................................14</div><div class="t m0 x15 h5 y1e ff3 fs2 fc1 sc0 ls0 ws0">2.2.7. <span class="ff2">时钟乘法和除法</span>..........................................................................................<span class="_ _4"></span>18</div><div class="t m0 x15 h5 y1f ff3 fs2 fc1 sc0 ls0 ws0">2.2.8. <span class="ff2">可编程相移</span>...............................................................................................<span class="_ _1"> </span>19</div><div class="t m0 x15 h5 y20 ff3 fs2 fc1 sc0 ls0 ws0">2.2.9. <span class="ff2">可编程占空比</span>............................................................................................<span class="_"> </span>19</div><div class="t m0 x15 h5 y21 ff3 fs2 fc1 sc0 ls0 ws0">2.2.10. PLL<span class="_ _1"> </span><span class="ff2">级联</span>................................................................................................<span class="_ _1"> </span>19</div><div class="t m0 x15 h5 y22 ff3 fs2 fc1 sc0 ls0 ws0">2.2.11. PLL<span class="_ _1"> </span><span class="ff2">输入时钟切换</span>.....................................................................................<span class="_ _5"> </span>20</div><div class="t m0 x15 h5 y23 ff3 fs2 fc1 sc0 ls0 ws0">2.2.12. PLL<span class="_ _1"> </span><span class="ff2">重配置和动态相移</span>................................................................................<span class="_ _6"></span>24</div><div class="t m0 x15 h5 y24 ff3 fs2 fc1 sc0 ls0 ws0">2.2.13. PLL<span class="_ _1"> </span><span class="ff2">校准</span>................................................................................................<span class="_ _1"> </span>24</div><div class="t m0 xf h5 y25 ff1 fs2 fc1 sc0 ls0 ws0">3. Intel Agilex <span class="ff2 sc2">时钟和<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2 sc2">设计考量</span>.......................................................................................<span class="_ _6"> </span>26</div><div class="t m0 x14 h5 y26 ff3 fs2 fc1 sc0 ls0 ws0">3.1. <span class="ff2">指南：时钟切换</span>......................................................................................................26</div><div class="t m0 x14 h5 y27 ff3 fs2 fc1 sc0 ls0 ws0">3.2. <span class="ff2">指南：时序收敛</span>......................................................................................................27</div><div class="t m0 x14 h5 y28 ff3 fs2 fc1 sc0 ls0 ws0">3.3. <span class="ff2">指南：复位<span class="_ _1"> </span></span>PLL......................................................................................................<span class="_ _4"></span>27</div><div class="t m0 x14 h5 y29 ff3 fs2 fc1 sc0 ls0 ws0">3.4. <span class="ff2">指南：配置约束</span>......................................................................................................27</div><div class="t m0 x14 h5 y2a ff3 fs2 fc1 sc0 ls0 ws0">3.5. <span class="ff2">指南：</span>I/O PLL<span class="_ _1"> </span><span class="ff2">重配置</span>.............................................................................................<span class="_ _2"> </span>27</div><div class="t m0 x14 h5 y2b ff3 fs2 fc1 sc0 ls0 ws0">3.6. <span class="ff2">时钟约束</span>..............................................................................................................<span class="_ _6"></span>28</div><div class="t m0 x14 h5 y2c ff3 fs2 fc1 sc0 ls0 ws0">3.7. IP<span class="_ _1"> </span><span class="ff2">核约束</span>.............................................................................................................<span class="_ _3"> </span>28</div><div class="t m0 x14 h9 y2d ff3 fs2 fc1 sc0 ls0 ws0">3.8. <span class="ff2">指南：使用从<span class="_ _1"> </span></span>L<span class="_ _7"></span>VDS SERDES Intel FPGA IP<span class="_ _1"> </span><span class="ff2">来的<span class="_ _1"> </span><span class="ff4 fs5">tx_outclk<span class="_ _1"> </span></span>端口，实现<span class="_ _1"> </span></span>f</div><div class="t m0 x16 h6 y2e ff3 fs3 fc1 sc0 ls0 ws0">OUT_EXT</div><div class="t m0 x17 h5 y2d ff3 fs2 fc1 sc0 ls0 ws0"> <span class="ff2">≥</span> 300</div><div class="t m0 x15 h5 y2f ff3 fs2 fc1 sc0 ls0 ws0">Mhz<span class="_ _1"> </span><span class="ff2">的<span class="_ _1"> </span></span>5%<span class="ff2">占空比</span>................................................................................................28</div><div class="t m0 xf h5 y30 ff1 fs2 fc1 sc0 ls0 ws0">4. Clock Control Intel FPGA IP<span class="_ _1"> </span><span class="ff2 sc2">核</span>......................................................................................<span class="_ _3"> </span>29</div><div class="t m0 x14 h5 y31 ff3 fs2 fc1 sc0 ls0 ws0">4.1. Clock Control Intel FPGA IP<span class="_ _1"> </span><span class="ff2">的发布信息</span>....................................................................<span class="_ _4"></span>29</div><div class="t m0 x14 h5 y32 ff3 fs2 fc1 sc0 ls0 ws0">4.2. Clock Control IP<span class="_ _1"> </span><span class="ff2">核参数</span>.........................................................................................<span class="_ _6"></span>29</div><div class="t m0 x14 h5 y33 ff3 fs2 fc1 sc0 ls0 ws0">4.3. Clock Control IP<span class="_ _1"> </span><span class="ff2">核端口和信号</span>.................................................................................30</div><div class="t m0 xf h5 y34 ff1 fs2 fc1 sc0 ls0 ws0">5. IOPLL Intel FPGA IP<span class="_ _1"> </span><span class="ff2 sc2">核</span>.................................................................................................<span class="_ _1"> </span>31</div><div class="t m0 x14 h5 y35 ff3 fs2 fc1 sc0 ls0 ws0">5.1. IOPLL Intel FPGA IP<span class="_ _1"> </span><span class="ff2">的发布信息</span>..............................................................................<span class="_ _3"> </span>31</div><div class="t m0 x14 h5 y36 ff3 fs2 fc1 sc0 ls0 ws0">5.2. .mif<span class="_ _1"> </span><span class="ff2">文件生成</span>........................................................................................................<span class="_ _6"></span>31</div><div class="t m0 x15 h5 y37 ff3 fs2 fc1 sc0 ls0 ws0">5.2.1. <span class="ff2">生成一个新的</span>.mif<span class="_ _1"> </span><span class="ff2">文件</span>.................................................................................<span class="_ _6"> </span>32</div><div class="t m0 x15 h5 y38 ff3 fs2 fc1 sc0 ls0 ws0">5.2.2. <span class="ff2">对现有</span>.mif<span class="_ _1"> </span><span class="ff2">文件添加配置</span>..............................................................................<span class="_ _3"> </span>32</div><div class="t m0 x14 h5 y39 ff3 fs2 fc1 sc0 ls0 ws0">5.3. IP-<span class="_ _7"></span>XACT<span class="_ _1"> </span><span class="ff2">文件生成</span>..................................................................................................<span class="_ _8"> </span>32</div><div class="t m2 x18 ha y3a ff2 fs6 fc1 sc2 ls0 ws0">内容</div><div class="t m0 xf hb y3b ff3 fs7 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 x19 hc y3c ff3 fs8 fc1 sc0 ls0 ws0">®</div><div class="t m0 x1a hb y3b ff3 fs7 fc1 sc0 ls0 ws0"> Agilex</div><div class="t m0 x1b hc y3c ff3 fs8 fc1 sc0 ls0 ws0">™</div><div class="t m0 x1c hd y3b ff2 fs7 fc1 sc0 ls0 ws0">时钟和<span class="_ _3"> </span><span class="ff3">PLL<span class="_ _3"> </span></span>用户指南</div><div class="t m0 x1d hd y3d ff2 fs7 fc0 sc1 ls0 ws0">发送反馈</div><div class="t m0 xf hb y3e ff3 fs7 fc1 sc0 ls0 ws0">2</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/bg3.jpg"><div class="t m0 x2 h5 y3f ff3 fs2 fc1 sc0 ls0 ws0">5.3.1. <span class="ff2">生成一个新的<span class="_ _1"> </span></span>IP-<span class="_ _7"></span>XACT<span class="_ _1"> </span><span class="ff2">文件</span>..........................................................................<span class="_ _5"> </span>32</div><div class="t m0 x1e h5 y40 ff3 fs2 fc1 sc0 ls0 ws0">5.4. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数</span>...................................................................................................<span class="_ _3"> </span>32</div><div class="t m0 x2 h5 y41 ff3 fs2 fc1 sc0 ls0 ws0">5.4.1. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数：</span>PLL<span class="_ _1"> </span><span class="ff2">选项卡</span>.......................................................................<span class="_ _6"></span>33</div><div class="t m0 x2 h5 y42 ff3 fs2 fc1 sc0 ls0 ws0">5.4.2. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数：</span>Settings<span class="_ _1"> </span><span class="ff2">选项卡</span>................................................................<span class="_ _1"> </span>35</div><div class="t m0 x2 h5 y43 ff3 fs2 fc1 sc0 ls0 ws0">5.4.3. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数：</span>Cascading<span class="_ _1"> </span><span class="ff2">选项卡</span>..............................................................36</div><div class="t m0 x2 h5 y44 ff3 fs2 fc1 sc0 ls0 ws0">5.4.4. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数</span> - Dynamic R<span class="_ _7"></span>econfiguration<span class="_ _1"> </span><span class="ff2">选项卡</span>.........................................<span class="_ _4"></span>36</div><div class="t m0 x2 h5 y45 ff3 fs2 fc1 sc0 ls0 ws0">5.4.5. IOPLL IP<span class="_ _1"> </span><span class="ff2">核参数</span> - Advanced P<span class="_ _7"></span>arameters<span class="_ _1"> </span><span class="ff2">选项卡</span>.............................................<span class="_ _3"> </span>37</div><div class="t m0 x1e h5 y46 ff3 fs2 fc1 sc0 ls0 ws0">5.5. IOPLL IP<span class="_ _1"> </span><span class="ff2">核端口和信号</span>...........................................................................................<span class="_ _8"> </span>37</div><div class="t m0 x1 h5 y47 ff1 fs2 fc1 sc0 ls0 ws0">6. Intel FPGA IP<span class="_ _1"> </span><span class="ff2 sc2">核</span>............................................................................................................<span class="_ _4"></span>39</div><div class="t m0 x1e h5 y48 ff3 fs2 fc1 sc0 ls0 ws0">6.1. IOPLL Reconfig <span class="_ _7"></span>Intel FPGA IP<span class="_ _1"> </span><span class="ff2">的发布信息</span>.................................................................<span class="_"> </span>39</div><div class="t m0 x1e h5 y49 ff3 fs2 fc1 sc0 ls0 ws0">6.2. <span class="ff2">实现<span class="_ _1"> </span></span>IOPLL Reconfig IP<span class="_ _3"> </span><span class="ff2">核中的<span class="_ _1"> </span></span>I/O PLL<span class="_ _1"> </span><span class="ff2">重配置</span>.............................................................<span class="_ _2"> </span>40</div><div class="t m0 x2 h5 y4a ff3 fs2 fc1 sc0 ls0 ws0">6.2.1. IOPLL<span class="_ _1"> </span><span class="ff2">与<span class="_ _1"> </span></span>IOPLL R<span class="_ _7"></span>econfig IP<span class="_ _1"> </span><span class="ff2">核之间的连接</span>......................................................<span class="_ _1"> </span>40</div><div class="t m0 x2 h5 y4b ff3 fs2 fc1 sc0 ls0 ws0">6.2.2. <span class="ff2">连接<span class="_ _1"> </span></span>IOPLL<span class="_ _1"> </span><span class="ff2">和<span class="_ _1"> </span></span>IOPLL Reconfig<span class="_ _7"></span> IP<span class="_ _1"> </span><span class="ff2">核</span>...............................................................<span class="_ _4"></span>40</div><div class="t m0 x1e h5 y4c ff3 fs2 fc1 sc0 ls0 ws0">6.3. IOPLL Reconfig <span class="_ _7"></span>IP<span class="_ _1"> </span><span class="ff2">核重配置模式</span>..............................................................................<span class="_ _1"> </span>41</div><div class="t m0 x2 h5 y4d ff3 fs2 fc1 sc0 ls0 ws0">6.3.1. .mif<span class="_ _1"> </span><span class="ff2">流重配置</span>............................................................................................<span class="_ _6"></span>41</div><div class="t m0 x2 h5 y4e ff3 fs2 fc1 sc0 ls0 ws0">6.3.2. <span class="ff2">高级模式重配置</span>..........................................................................................<span class="_ _4"></span>42</div><div class="t m0 x2 h5 y4f ff3 fs2 fc1 sc0 ls0 ws0">6.3.3. <span class="ff2">时钟门控重新配置</span>.......................................................................................<span class="_ _8"> </span>43</div><div class="t m0 x2 h5 y50 ff3 fs2 fc1 sc0 ls0 ws0">6.3.4. <span class="ff2">动态相移重配置</span>..........................................................................................<span class="_ _4"></span>43</div><div class="t m0 x1e h5 y51 ff3 fs2 fc1 sc0 ls0 ws0">6.4. IOPLL Reconfig <span class="_ _7"></span>IP<span class="_ _1"> </span><span class="ff2">核中的<span class="_ _1"> </span></span>Avalon Memory<span class="_ _7"></span>-Mapped Interface<span class="_ _1"> </span><span class="ff2">端口</span>.................................<span class="_ _9"> </span>43</div><div class="t m0 x1e h5 y52 ff3 fs2 fc1 sc0 ls0 ws0">6.5. <span class="ff2">地址总线核数据总线设置</span>...........................................................................................<span class="_ _4"></span>44</div><div class="t m0 x2 h5 y53 ff3 fs2 fc1 sc0 ls0 ws0">6.5.1. <span class="ff2">高级模式重配置的地址总线和数据总线设置</span>.........................................................<span class="_ _4"></span>44</div><div class="t m0 x2 h5 y54 ff3 fs2 fc1 sc0 ls0 ws0">6.5.2. <span class="ff2">针对时钟门控重配置的输出时钟和相应数据位设置</span>................................................<span class="_"> </span>50</div><div class="t m0 x2 h5 y55 ff3 fs2 fc1 sc0 ls0 ws0">6.5.3. <span class="ff2">针对<span class="_ _1"> </span></span>IOPLL Reconfig<span class="_ _7"></span> IP<span class="_ _1"> </span><span class="ff2">核动态相移的数据总线设置</span>.............................................<span class="_ _4"></span>51</div><div class="t m0 x1e h5 y56 ff3 fs2 fc1 sc0 ls0 ws0">6.6. <span class="ff2">设计实例</span>..............................................................................................................<span class="_ _6"></span>51</div><div class="t m0 x2 h5 y57 ff3 fs2 fc1 sc0 ls0 ws0">6.6.1. <span class="ff2">重配置选项：使用<span class="_ _1"> </span></span>IOPLL Reconfig<span class="_ _7"></span> IP<span class="_ _1"> </span><span class="ff2">核的</span>.mif<span class="_ _1"> </span><span class="ff2">流重配置</span>......................................<span class="_"> </span>52</div><div class="t m0 x2 h5 y58 ff3 fs2 fc1 sc0 ls0 ws0">6.6.2. <span class="ff2">重配置选项：使用<span class="_ _1"> </span></span>IOPLL Reconfig<span class="_ _7"></span> IP<span class="_ _1"> </span><span class="ff2">核的高级模式重配置和重新校准</span>.......................<span class="_ _4"></span>52</div><div class="t m0 x2 h5 y59 ff3 fs2 fc1 sc0 ls0 ws0">6.6.3. <span class="ff2">重配置选项：使用<span class="_ _1"> </span></span>IOPLL Reconfig<span class="_ _7"></span> IP<span class="_ _1"> </span><span class="ff2">核的时钟门控重配置</span>....................................<span class="_ _2"> </span>53</div><div class="t m0 x1 h5 y5a ff1 fs2 fc1 sc0 ls0 ws0">7. Intel Agilex <span class="ff2 sc2">时钟和<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2 sc2">用户指南存档</span>.................................................................................<span class="_ _5"> </span>54</div><div class="t m0 x1 h5 y5b ff1 fs2 fc1 sc0 ls0 ws0">8. Intel Agilex <span class="ff2 sc2">时钟和<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2 sc2">用户指南文档修订历史</span>......................................................................<span class="_ _1"> </span>55</div><div class="t m2 x1 ha y5c ff2 fs6 fc1 sc2 ls0 ws0">内容</div><div class="t m0 xb hd y3d ff2 fs7 fc0 sc1 ls0 ws0">发送反馈</div><div class="t m0 x1f hb y3b ff3 fs7 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 x20 hc y3c ff3 fs8 fc1 sc0 ls0 ws0">®</div><div class="t m0 x21 hb y3b ff3 fs7 fc1 sc0 ls0 ws0"> Agilex</div><div class="t m0 x22 hc y3c ff3 fs8 fc1 sc0 ls0 ws0">™</div><div class="t m0 x23 hd y3b ff2 fs7 fc1 sc0 ls0 ws0">时钟和<span class="_ _3"> </span><span class="ff3">PLL<span class="_ _9"> </span></span>用户指南</div><div class="t m0 x24 hb y3e ff3 fs7 fc1 sc0 ls0 ws0">3</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/bg4.jpg"><div class="t m0 xf he y5d ff1 fs4 fc0 sc0 ls0 ws0">1. Intel</div><div class="t m0 x25 hf y5e ff1 fs9 fc0 sc0 ls0 ws0">®</div><div class="t m0 x26 he y5d ff1 fs4 fc0 sc0 ls0 ws0"> Agilex</div><div class="t m0 x27 hf y5e ff1 fs9 fc0 sc0 ls0 ws0">™</div><div class="t m0 x28 h8 y5d ff1 fs4 fc0 sc0 ls0 ws0"> <span class="ff2 sc1">时钟和<span class="_ _a"> </span></span>PLL<span class="_ _a"> </span><span class="ff2 sc1">概述</span></div><div class="t m0 xf h10 y5f ff1 fsa fc0 sc0 ls0 ws0">1.1. <span class="ff2 sc1">时钟网络概述</span></div><div class="t m0 x29 h7 y60 ff3 fs2 fc1 sc0 ls0 ws0">Intel</div><div class="t m0 x2a h6 y61 ff3 fs3 fc1 sc0 ls0 ws0">®</div><div class="t m0 x2b h7 y60 ff3 fs2 fc1 sc0 ls0 ws0"> Agilex</div><div class="t m0 x2c h6 y61 ff3 fs3 fc1 sc0 ls0 ws0">™</div><div class="t m0 x2d h5 y60 ff3 fs2 fc1 sc0 ls0 ws0"> <span class="ff2">器件包含将信号分布到整个架构的专用资源。通常，这些资源用于时钟信号，也可</span></div><div class="t m0 x29 h5 y62 ff2 fs2 fc1 sc0 ls0 ws0">以用于那些要求低偏移的其他信号。在<span class="ff3"> Intel Agilex </span>器件中，这些资源作为可编程的时钟布线实</div><div class="t m0 x29 h5 y63 ff2 fs2 fc1 sc0 ls0 ws0">现，并允许用于各种规模的低偏移时钟树的实现。</div><div class="t m0 x29 h5 y64 ff2 fs2 fc0 sc1 ls0 ws0">相关链接</div><div class="t m0 x29 h5 y65 ff2 fs2 fc0 sc0 ls0 ws0">使用全局时钟网络资源，<span class="ff3">Intel Quartus</span></div><div class="t m0 x2e h6 y66 ff3 fs3 fc0 sc0 ls0 ws0">®</div><div class="t m0 x2f h5 y65 ff3 fs2 fc0 sc0 ls0 ws0"> Prime Pro Edition<span class="_ _1"> </span><span class="ff2">用户指南：设计建议</span></div><div class="t m0 x30 h5 y67 ff2 fs2 fc1 sc0 ls0 ws0">提供有关<span class="_ _1"> </span><span class="ff3">Intel Quartus</span></div><div class="t m0 x31 h6 y68 ff3 fs3 fc1 sc0 ls0 ws0">®</div><div class="t m0 x32 h5 y67 ff3 fs2 fc1 sc0 ls0 ws0"> Prime<span class="_ _1"> </span><span class="ff2">软件中时钟分配的更多信息。</span></div><div class="t m0 xf h10 y69 ff1 fsa fc0 sc0 ls0 ws0">1.2. PLL<span class="_ _b"> </span><span class="ff2 sc1">概述</span></div><div class="t m0 x29 h5 y6a ff2 fs2 fc1 sc0 ls0 ws0">锁相环（<span class="ff3">PLL</span>）对器件时钟管理、外部系统时钟管理以及高速<span class="_ _1"> </span><span class="ff3">I/O<span class="_ _1"> </span></span>接口提供强健的时钟管理与综合。</div><div class="t m0 x29 h5 y6b ff3 fs2 fc1 sc0 ls0 ws0">Intel Agilex <span class="ff2">器件系列包含以下<span class="_ _1"> </span></span>I/O PLL<span class="_ _1"> </span><span class="ff2">用于内核应用程序。</span>I/O PLL<span class="_ _1"> </span><span class="ff2">只能用作整数<span class="_ _1"> </span></span>PLL<span class="ff2">。</span></div><div class="t m0 x29 h11 y6c ff5 fs2 fc1 sc0 ls0 ws0">•<span class="_ _c"> </span><span class="ff3">F<span class="_ _7"></span>abric-feeding I/O PLLs<span class="ff2">—有<span class="_ _1"> </span></span>3<span class="_ _1"> </span><span class="ff2">个<span class="_ _1"> </span><span class="ff4 fs5">C<span class="_ _1"> </span></span>计数器输出可用，不支持<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2">级联。</span></span></div><div class="t m0 x29 h11 y6d ff5 fs2 fc1 sc0 ls0 ws0">•<span class="_ _c"> </span><span class="ff3">I/O bank I/O PLLs<span class="ff2">—有<span class="_ _1"> </span></span>7<span class="_ _1"> </span><span class="ff2">个<span class="_ _1"> </span><span class="ff4 fs5">C<span class="_ _1"> </span></span>计数器输出可用，不支持<span class="_ _1"> </span></span>PLL<span class="_ _1"> </span><span class="ff2">级联</span></span></div><div class="t m0 x29 h5 y6e ff3 fs2 fc1 sc0 ls0 ws0">I/O PLL<span class="_ _1"> </span><span class="ff2">在与<span class="_ _1"> </span></span>I/O Bank<span class="_ _1"> </span><span class="ff2">中的硬存储控制器和<span class="_ _1"> </span></span>L<span class="_ _7"></span>VDS<span class="_ _1"> </span><span class="ff2">串化器</span>/<span class="ff2">解串器</span> (SERDES) <span class="ff2">块相邻的位置。每</span></div><div class="t m0 x29 h5 y6f ff2 fs2 fc1 sc0 ls0 ws0">个<span class="_ _1"> </span><span class="ff3">I/O bank<span class="_ _1"> </span></span>包含<span class="_ _1"> </span><span class="ff3">2<span class="_ _1"> </span></span>个<span class="_ _1"> </span><span class="ff3">I/O bank I/O PLL<span class="_ _1"> </span></span>和一个架构馈给<span class="_ _1"> </span><span class="ff3">I/O PLL</span>。</div><div class="t m0 x1 hb y70 ff1 fs7 fc0 sc0 ls0 ws0">683761 | 2021.12.13</div><div class="t m0 xb hd y71 ff2 fs7 fc0 sc1 ls0 ws0">发送反馈</div><div class="t m0 x33 hd y72 ff2 fs7 fc1 sc0 ls1 ws0">英特尔公司。保留所有权利<span class="ls0">。英特尔<span class="_ _4"></span>、</span>英特尔徽标和其他英特尔标志是英特尔公司或其子公司的商标。依照英特尔的标准保证条</div><div class="t m0 x33 hd y73 ff2 fs7 fc1 sc0 ls0 ws0">例，<span class="ls2">英特尔保证其<span class="_ _3"> </span></span><span class="ff3">FPGA<span class="_ _3"> </span></span><span class="ls2">和半导体产品的性能符合当前规格，但保留随时更改任何产品和服务的权利，恕不另行通知</span>。英特尔概</div><div class="t m0 x33 hd y74 ff2 fs7 fc1 sc0 ls1 ws0">不承担因应用或使用本文中描述的任何信息、产品或服务而产生的任何责任和义务，除非得到英特尔书面上的明确同意<span class="ls0">。建议英</span></div><div class="t m0 x33 hd y75 ff2 fs7 fc1 sc0 ls0 ws0">特尔客户在信赖任何已发布的信息之前以及下单订购产品或服务之前，应先获取最新版本的器件规格。</div><div class="t m0 x33 hd y76 ff3 fs7 fc1 sc0 ls0 ws0">*<span class="ff2">其他的名称和品牌可能是其他所有者的资产。</span></div><div class="t m0 x34 hb y77 ff1 fs7 fc0 sc0 ls0 ws0">ISO</div><div class="t m0 x34 hb y78 ff1 fs7 fc0 sc0 ls0 ws0">9001:2015</div><div class="t m0 x34 hb y79 ff1 fs7 fc0 sc0 ls0 ws0">Registered</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90014976/bg5.jpg"><div class="t m0 xf h8 y5d ff1 fs4 fc0 sc0 ls0 ws0">2. Intel Agilex <span class="ff2 sc1">时钟和<span class="_ _a"> </span></span>PLL<span class="_ _a"> </span><span class="ff2 sc1">架构和功能特性</span></div><div class="t m0 xf h10 y5f ff1 fsa fc0 sc0 ls0 ws0">2.1. <span class="ff2 sc1">时钟网络架构和功能特性</span></div><div class="t m0 xf h12 y7a ff1 fsb fc0 sc0 ls0 ws0">2.1.1. <span class="ff2 sc1">时钟网络架构</span></div><div class="t m0 x29 h5 y7b ff2 fs2 fc1 sc0 ls0 ws0">每个<span class="ff3"> Intel Agilex </span>器件被分成一些大小均匀的时钟区域（<span class="ff3">clock sector</span>）。</div><div class="t m0 xf h5 y7c ff2 fs2 fc0 sc1 ls0 ws0">图<span class="ff1 sc0"> 1.</span></div><div class="t m0 x35 h5 y7d ff1 fs2 fc0 sc0 ls0 ws0">Intel Agilex <span class="ff2 sc1">器件的时钟区域</span>(clock sector)<span class="ff2 sc1">平面图</span></div><div class="t m0 x29 hd y7e ff2 fs7 fc1 sc0 ls0 ws0">该图显示<span class="ff3"> Intel Agilex </span>器件中的时钟区域示例，<span class="ff3"> </span>其中的时钟区域以阵列实现—本示例中为<span class="_ _3"> </span><span class="ff3">5<span class="_ _9"> </span></span>行和<span class="_ _3"> </span><span class="ff3">6<span class="_ _3"> </span></span>列。<span class="ff3">I/O bank<span class="_ _3"> </span></span>位于<span class="ff3"> Intel</span></div><div class="t m0 x29 hd y7f ff3 fs7 fc1 sc0 ls0 ws0">Agilex <span class="ff2">器件的顶部和底部。</span></div><div class="c x36 y80 w2 h13"><div class="t m0 x37 h14 y81 ff6 fs9 fc1 sc0 ls0 ws0">Clock Sector</div><div class="t m0 x37 h15 y82 ff6 fs9 fc1 sc0 ls0 ws0">I/O Bank<span class="ff2">行</span></div><div class="t m0 x38 h15 y83 ff6 fs9 fc1 sc0 ls0 ws0">I/O Bank<span class="ff2">行</span></div></div><div class="t m0 xf h16 y84 ff1 fs5 fc0 sc0 ls0 ws0">2.1.1.1. <span class="ff2 sc1">时钟网络层次</span></div><div class="t m0 x29 h5 y85 ff3 fs2 fc1 sc0 ls0 ws0">Intel Agilex <span class="ff2">时钟网络以一个<span class="_ _1"> </span></span>3<span class="_ _1"> </span><span class="ff2">级的层次组织而成。</span></div><div class="t m0 xf h5 y86 ff2 fs2 fc0 sc1 ls0 ws0">图<span class="ff1 sc0"> 2.</span></div><div class="t m0 x35 h5 y87 ff2 fs2 fc0 sc1 ls0 ws0">时钟网络层次</div><div class="c x9 y88 w3 h17"><div class="t m0 x39 h18 y89 ff7 fsc fc2 sc0 ls0 ws0">Progr<span class="_ _7"></span>ammable</div><div class="t m0 x3a h18 y8a ff7 fsc fc2 sc0 ls0 ws0">Clock Routing</div><div class="t m0 x3b h18 y8b ff7 fsc fc2 sc0 ls0 ws0">SCLK</div><div class="t m0 x3c h14 y8c ff7 fs9 fc2 sc0 ls0 ws0">6<span class="_ _d"></span>32</div><div class="t m0 x25 h14 y8d ff7 fs9 fc2 sc0 ls0 ws0">32</div><div class="t m0 x3d h18 y8e ff7 fsc fc2 sc0 ls0 ws0">Row Clock</div><div class="t m0 x3e h18 y8f ff7 fsc fc2 sc0 ls0 ws0">First L<span class="_ _7"></span>evel<span class="_ _e"> </span>Second Lev<span class="_ _7"></span>el<span class="_ _f"> </span>Thir<span class="_ _7"></span>d Level</div><div class="t m0 x0 h18 y90 ff7 fsc fc2 sc0 ls0 ws0">Clock Source</div></div><div class="t m0 x1 hb y91 ff1 fs7 fc0 sc0 ls0 ws0">683761 | 2021.12.13</div><div class="t m0 xb hd y71 ff2 fs7 fc0 sc1 ls0 ws0">发送反馈</div><div class="t m0 x33 hd y72 ff2 fs7 fc1 sc0 ls1 ws0">英特尔公司。保留所有权利<span class="ls0">。英特尔<span class="_ _4"></span>、</span>英特尔徽标和其他英特尔标志是英特尔公司或其子公司的商标。依照英特尔的标准保证条</div><div class="t m0 x33 hd y73 ff2 fs7 fc1 sc0 ls0 ws0">例，<span class="ls2">英特尔保证其<span class="_ _3"> </span></span><span class="ff3">FPGA<span class="_ _3"> </span></span><span class="ls2">和半导体产品的性能符合当前规格，但保留随时更改任何产品和服务的权利，恕不另行通知</span>。英特尔概</div><div class="t m0 x33 hd y74 ff2 fs7 fc1 sc0 ls1 ws0">不承担因应用或使用本文中描述的任何信息、产品或服务而产生的任何责任和义务，除非得到英特尔书面上的明确同意<span class="ls0">。建议英</span></div><div class="t m0 x33 hd y75 ff2 fs7 fc1 sc0 ls0 ws0">特尔客户在信赖任何已发布的信息之前以及下单订购产品或服务之前，应先获取最新版本的器件规格。</div><div class="t m0 x33 hd y76 ff3 fs7 fc1 sc0 ls0 ws0">*<span class="ff2">其他的名称和品牌可能是其他所有者的资产。</span></div><div class="t m0 x34 hb y77 ff1 fs7 fc0 sc0 ls0 ws0">ISO</div><div class="t m0 x34 hb y78 ff1 fs7 fc0 sc0 ls0 ws0">9001:2015</div><div class="t m0 x34 hb y79 ff1 fs7 fc0 sc0 ls0 ws0">Registered</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>